CSRNG Simulation Results

Friday April 18 2025 17:34:30 UTC

GitHub Revision: `97d23b4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	10.000s	285.583us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	6.000s	60.196us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	52.421us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	22.000s	948.341us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	10.000s	488.343us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	132.622us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	52.421us	20	20	100.00
		csrng_csr_aliasing	10.000s	488.343us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	22.000s	1.455ms	199	200	99.50
V2	alerts	csrng_alert	47.000s	2.852ms	500	500	100.00
V2	err	csrng_err	8.000s	24.366us	499	500	99.80
V2	cmds	csrng_cmds	6.917m	38.718ms	50	50	100.00
V2	life cycle	csrng_cmds	6.917m	38.718ms	50	50	100.00
V2	stress_all	csrng_stress_all	25.500m	117.917ms	47	50	94.00
V2	intr_test	csrng_intr_test	6.000s	102.560us	50	50	100.00
V2	alert_test	csrng_alert_test	8.000s	192.656us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	21.000s	1.075ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	21.000s	1.075ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	6.000s	60.196us	5	5	100.00
		csrng_csr_rw	6.000s	52.421us	20	20	100.00
		csrng_csr_aliasing	10.000s	488.343us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	172.655us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	6.000s	60.196us	5	5	100.00
		csrng_csr_rw	6.000s	52.421us	20	20	100.00
		csrng_csr_aliasing	10.000s	488.343us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	172.655us	20	20	100.00
V2		TOTAL			1435	1440	99.65
V2S	tl_intg_err	csrng_sec_cm	8.000s	102.969us	5	5	100.00
		csrng_tl_intg_err	22.000s	2.023ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	6.000s	15.018us	50	50	100.00
		csrng_csr_rw	6.000s	52.421us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	47.000s	2.852ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	25.500m	117.917ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	22.000s	1.455ms	199	200	99.50
		csrng_err	8.000s	24.366us	499	500	99.80
		csrng_sec_cm	8.000s	102.969us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	22.000s	1.455ms	199	200	99.50
		csrng_err	8.000s	24.366us	499	500	99.80
		csrng_sec_cm	8.000s	102.969us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	22.000s	1.455ms	199	200	99.50
		csrng_err	8.000s	24.366us	499	500	99.80
		csrng_sec_cm	8.000s	102.969us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	22.000s	1.455ms	199	200	99.50
		csrng_err	8.000s	24.366us	499	500	99.80
		csrng_sec_cm	8.000s	102.969us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	22.000s	1.455ms	199	200	99.50
		csrng_err	8.000s	24.366us	499	500	99.80
		csrng_sec_cm	8.000s	102.969us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	22.000s	1.455ms	199	200	99.50
		csrng_err	8.000s	24.366us	499	500	99.80
		csrng_sec_cm	8.000s	102.969us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	22.000s	1.455ms	199	200	99.50
		csrng_err	8.000s	24.366us	499	500	99.80
		csrng_sec_cm	8.000s	102.969us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	47.000s	2.852ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	22.000s	1.455ms	199	200	99.50
		csrng_err	8.000s	24.366us	499	500	99.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	25.500m	117.917ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	47.000s	2.852ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	22.000s	2.023ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	22.000s	1.455ms	199	200	99.50
		csrng_err	8.000s	24.366us	499	500	99.80
		csrng_sec_cm	8.000s	102.969us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	22.000s	1.455ms	199	200	99.50
		csrng_err	8.000s	24.366us	499	500	99.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	22.000s	1.455ms	199	200	99.50
		csrng_err	8.000s	24.366us	499	500	99.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	22.000s	1.455ms	199	200	99.50
		csrng_err	8.000s	24.366us	499	500	99.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	22.000s	1.455ms	199	200	99.50
		csrng_err	8.000s	24.366us	499	500	99.80
		csrng_sec_cm	8.000s	102.969us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	22.000s	1.455ms	199	200	99.50
		csrng_err	8.000s	24.366us	499	500	99.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.950m	5.372ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1615	1630	99.08

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.75	98.61	96.63	99.94	97.30	92.08	100.00	97.36	90.82

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:925) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test csrng_stress_all_with_rand_reset has 9 failures.
  - 0.csrng_stress_all_with_rand_reset.39581449774529518948448042493051920446082036560162809462200950805666619062569
    Line 105, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6897907243 ps: (cip_base_vseq.sv:925) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6897907243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.csrng_stress_all_with_rand_reset.94251387110650379793233435525938462026604453323100565278325789381321017386734
    Line 111, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1133081199 ps: (cip_base_vseq.sv:925) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1133081199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:

Test csrng_stress_all has 3 failures.

13.csrng_stress_all.32299064498146994895331402067712954408734431949731145499867378049526950196801
Line 143, in log /nightly/runs/scratch/master/csrng-sim-xcelium/13.csrng_stress_all/latest/run.log

  UVM_ERROR @  27874120 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  27874120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.csrng_stress_all.113269448271624413353497858343297571170055218932931318813270194766406230638135
Line 138, in log /nightly/runs/scratch/master/csrng-sim-xcelium/19.csrng_stress_all/latest/run.log

  UVM_ERROR @ 2904117298 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 2904117298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 4.csrng_stress_all_with_rand_reset.82021363729043357824518572476111198788828845713423687662221945649172722766154
    Line 107, in log /nightly/runs/scratch/master/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  49924715 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @  49924715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 16.csrng_err.68354566259607849214709108178074268232541964497764211527392852579692201918436
    Line 133, in log /nightly/runs/scratch/master/csrng-sim-xcelium/16.csrng_err/latest/run.log
```
  UVM_ERROR @  13019505 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  13019505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 1 failures:

Test csrng_intr has 1 failures.

23.csrng_intr.85343387689932510499404883295366153817352073995672040181671619766457513803944
Line 133, in log /nightly/runs/scratch/master/csrng-sim-xcelium/23.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 153833196 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 153833196 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 153833196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---