DMA Simulation Results

Friday April 18 2025 17:34:30 UTC

GitHub Revision: 97d23b4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	11.000s	2.012ms	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	10.000s	1.300ms	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	12.000s	353.355us	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	42.000s	55.181us	5	5	100.00
V1	csr_rw	dma_csr_rw	42.000s	61.488us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	52.000s	2.643ms	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	47.000s	2.935ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	42.000s	29.725us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	42.000s	61.488us	20	20	100.00
		dma_csr_aliasing	47.000s	2.935ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.683m	17.718ms	5	5	100.00
V2	dma_handshake_stress	dma_handshake_stress	48.033m	220.903ms	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	6.683m	68.792ms	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	28.733m	323.630ms	4	5	80.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	48.033m	220.903ms	3	3	100.00
V2	dma_abort	dma_abort	13.000s	7.035ms	5	5	100.00
V2	dma_stress_all	dma_stress_all	5.483m	24.160ms	3	3	100.00
V2	intr_test	dma_intr_test	42.000s	12.603us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	43.000s	255.252us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	43.000s	255.252us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	42.000s	55.181us	5	5	100.00
		dma_csr_rw	42.000s	61.488us	20	20	100.00
		dma_csr_aliasing	47.000s	2.935ms	5	5	100.00
		dma_same_csr_outstanding	42.000s	86.114us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	42.000s	55.181us	5	5	100.00
		dma_csr_rw	42.000s	61.488us	20	20	100.00
		dma_csr_aliasing	47.000s	2.935ms	5	5	100.00
		dma_same_csr_outstanding	42.000s	86.114us	20	20	100.00
V2		TOTAL			113	114	99.12
V2S	dma_illegal_addr_range	dma_mem_enabled	34.000s	360.584us	5	5	100.00
		dma_generic_stress	28.733m	323.630ms	4	5	80.00
		dma_handshake_stress	48.033m	220.903ms	3	3	100.00
V2S	tl_intg_err	dma_tl_intg_err	44.000s	228.048us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	dma_short_transfer	2.967m	15.893ms	5	5	100.00
		dma_longer_transfer	7.000s	147.866us	5	5	100.00
		TOTAL			303	304	99.67

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
75.99	96.98	95.20	96.93	95.97	82.72	82.76	97.77	42.09

Failure Buckets

• Job timed out after * minutes has 1 failures:
  • Test dma_generic_stress has 1 failures.

    • 3.dma_generic_stress.46266508959247869285080017887034460065965093821885162396561693634103217048641
      Log /nightly/runs/scratch/master/dma-sim-xcelium/3.dma_generic_stress/latest/run.log

        Job timed out after 60 minutes