EDN Simulation Results

Friday April 18 2025 17:34:30 UTC

GitHub Revision: 97d23b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.580s 18.042us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 2.280s 23.604us 5 5 100.00
V1 csr_rw edn_csr_rw 2.540s 22.928us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.220s 262.366us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.560s 169.209us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.840s 28.182us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.540s 22.928us 20 20 100.00
edn_csr_aliasing 2.560s 169.209us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 56.020s 4.550ms 300 300 100.00
V2 csrng_commands edn_genbits 56.020s 4.550ms 300 300 100.00
V2 genbits edn_genbits 56.020s 4.550ms 300 300 100.00
V2 interrupts edn_intr 2.660s 21.047us 50 50 100.00
V2 alerts edn_alert 2.970s 30.770us 200 200 100.00
V2 errs edn_err 2.930s 29.794us 100 100 100.00
V2 disable edn_disable 2.520s 23.530us 50 50 100.00
edn_disable_auto_req_mode 2.770s 28.322us 50 50 100.00
V2 stress_all edn_stress_all 8.300s 382.724us 50 50 100.00
V2 intr_test edn_intr_test 3.010s 24.494us 50 50 100.00
V2 alert_test edn_alert_test 2.660s 57.786us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.430s 1.280ms 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.430s 1.280ms 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 2.280s 23.604us 5 5 100.00
edn_csr_rw 2.540s 22.928us 20 20 100.00
edn_csr_aliasing 2.560s 169.209us 5 5 100.00
edn_same_csr_outstanding 2.670s 37.859us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 2.280s 23.604us 5 5 100.00
edn_csr_rw 2.540s 22.928us 20 20 100.00
edn_csr_aliasing 2.560s 169.209us 5 5 100.00
edn_same_csr_outstanding 2.670s 37.859us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 9.030s 1.879ms 5 5 100.00
edn_tl_intg_err 4.280s 180.023us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 2.720s 19.317us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 2.970s 30.770us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 9.030s 1.879ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 9.030s 1.879ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 9.030s 1.879ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 9.030s 1.879ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.970s 30.770us 200 200 100.00
edn_sec_cm 9.030s 1.879ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.970s 30.770us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 4.280s 180.023us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.679m 8.904ms 31 50 62.00
V3 TOTAL 31 50 62.00
TOTAL 1111 1130 98.32

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.54 98.32 94.23 97.02 90.12 96.36 99.78 92.94

Failure Buckets