HMAC Simulation Results

Friday April 18 2025 17:34:30 UTC

GitHub Revision: 97d23b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	10.470s	1.471ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.380s	35.612us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.470s	63.452us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.080s	1.637ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.990s	904.799us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	5.759m	520.251ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.470s	63.452us	20	20	100.00
		hmac_csr_aliasing	9.990s	904.799us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.351m	10.764ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.352m	17.789ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	3.293m	6.648ms	30	30	100.00
		hmac_test_sha384_vectors	8.155m	57.896ms	75	75	100.00
		hmac_test_sha512_vectors	8.475m	47.767ms	75	75	100.00
		hmac_test_hmac256_vectors	13.330s	4.550ms	50	50	100.00
		hmac_test_hmac384_vectors	17.840s	779.784us	60	60	100.00
		hmac_test_hmac512_vectors	20.590s	1.661ms	75	75	100.00
V2	burst_wr	hmac_burst_wr	31.990s	1.552ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	19.550m	7.004ms	10	10	100.00
V2	error	hmac_error	1.062m	30.388ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.385m	14.697ms	10	10	100.00
V2	save_and_restore	hmac_smoke	10.470s	1.471ms	10	10	100.00
		hmac_long_msg	1.351m	10.764ms	10	10	100.00
		hmac_back_pressure	1.352m	17.789ms	25	25	100.00
		hmac_datapath_stress	19.550m	7.004ms	10	10	100.00
		hmac_burst_wr	31.990s	1.552ms	50	50	100.00
		hmac_stress_all	28.245m	45.132ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	10.470s	1.471ms	10	10	100.00
		hmac_long_msg	1.351m	10.764ms	10	10	100.00
		hmac_back_pressure	1.352m	17.789ms	25	25	100.00
		hmac_datapath_stress	19.550m	7.004ms	10	10	100.00
		hmac_wipe_secret	1.385m	14.697ms	10	10	100.00
		hmac_test_sha256_vectors	3.293m	6.648ms	30	30	100.00
		hmac_test_sha384_vectors	8.155m	57.896ms	75	75	100.00
		hmac_test_sha512_vectors	8.475m	47.767ms	75	75	100.00
		hmac_test_hmac256_vectors	13.330s	4.550ms	50	50	100.00
		hmac_test_hmac384_vectors	17.840s	779.784us	60	60	100.00
		hmac_test_hmac512_vectors	20.590s	1.661ms	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	10.470s	1.471ms	10	10	100.00
		hmac_long_msg	1.351m	10.764ms	10	10	100.00
		hmac_back_pressure	1.352m	17.789ms	25	25	100.00
		hmac_datapath_stress	19.550m	7.004ms	10	10	100.00
		hmac_burst_wr	31.990s	1.552ms	50	50	100.00
		hmac_error	1.062m	30.388ms	10	10	100.00
		hmac_wipe_secret	1.385m	14.697ms	10	10	100.00
		hmac_test_sha256_vectors	3.293m	6.648ms	30	30	100.00
		hmac_test_sha384_vectors	8.155m	57.896ms	75	75	100.00
		hmac_test_sha512_vectors	8.475m	47.767ms	75	75	100.00
		hmac_test_hmac256_vectors	13.330s	4.550ms	50	50	100.00
		hmac_test_hmac384_vectors	17.840s	779.784us	60	60	100.00
		hmac_test_hmac512_vectors	20.590s	1.661ms	75	75	100.00
		hmac_stress_all	28.245m	45.132ms	50	50	100.00
V2	stress_all	hmac_stress_all	28.245m	45.132ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.000s	33.143us	50	50	100.00
V2	intr_test	hmac_intr_test	2.080s	20.191us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.120s	77.973us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.120s	77.973us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.380s	35.612us	5	5	100.00
		hmac_csr_rw	2.470s	63.452us	20	20	100.00
		hmac_csr_aliasing	9.990s	904.799us	5	5	100.00
		hmac_same_csr_outstanding	3.770s	141.207us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.380s	35.612us	5	5	100.00
		hmac_csr_rw	2.470s	63.452us	20	20	100.00
		hmac_csr_aliasing	9.990s	904.799us	5	5	100.00
		hmac_same_csr_outstanding	3.770s	141.207us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	2.120s	248.135us	5	5	100.00
		hmac_tl_intg_err	5.580s	267.879us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.580s	267.879us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	10.470s	1.471ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	6.610s	351.785us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	8.604m	9.127ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	2.080s	71.629us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.06	100.00	97.14	100.00	100.00	100.00	100.00	47.30