97d23b4| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.188m | 7.388ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 39.720s | 1.698ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 2.200s | 43.103us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 2.310s | 32.188us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.250s | 341.274us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 3.160s | 447.765us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 2.980s | 140.890us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 2.310s | 32.188us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 3.160s | 447.765us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 16.150s | 2.274ms | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 44.330m | 183.839ms | 16 | 50 | 32.00 |
| V2 | host_maxperf | i2c_host_perf | 24.940m | 50.747ms | 49 | 50 | 98.00 |
| V2 | host_override | i2c_host_override | 2.210s | 30.653us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 4.227m | 40.046ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 2.395m | 2.630ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.790s | 355.124us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 24.710s | 646.395us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.380s | 229.188us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.087m | 9.151ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 36.600s | 1.244ms | 50 | 50 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 8.060s | 210.497us | 20 | 50 | 40.00 |
| V2 | target_glitch | i2c_target_glitch | 11.250s | 4.046ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 15.975m | 58.941ms | 50 | 50 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 8.720s | 983.689us | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.058m | 6.397ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 11.720s | 3.301ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 3.440s | 268.780us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 3.870s | 445.635us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 19.795m | 66.293ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.058m | 6.397ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 5.003m | 23.355ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 10.810s | 5.129ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 2.597m | 4.039ms | 43 | 50 | 86.00 |
| V2 | bad_address | i2c_target_bad_addr | 9.380s | 1.357ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 40.770s | 10.024ms | 25 | 50 | 50.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 4.890s | 5.939ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 3.230s | 416.460us | 48 | 50 | 96.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 24.940m | 50.747ms | 49 | 50 | 98.00 |
| i2c_host_perf_precise | 6.125m | 23.345ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 36.600s | 1.244ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 28.650s | 2.790ms | 49 | 50 | 98.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 5.280s | 623.066us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 4.950s | 1.090ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 3.280s | 678.864us | 29 | 50 | 58.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 24.620s | 2.669ms | 50 | 50 | 100.00 |
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 4.450s | 599.931us | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 2.250s | 53.819us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 2.260s | 37.039us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 4.190s | 156.084us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 4.190s | 156.084us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 2.200s | 43.103us | 5 | 5 | 100.00 |
| i2c_csr_rw | 2.310s | 32.188us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 3.160s | 447.765us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 2.670s | 110.734us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 2.200s | 43.103us | 5 | 5 | 100.00 |
| i2c_csr_rw | 2.310s | 32.188us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 3.160s | 447.765us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 2.670s | 110.734us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1671 | 1792 | 93.25 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 3.630s | 797.092us | 20 | 20 | 100.00 |
| i2c_sec_cm | 2.390s | 73.405us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 3.630s | 797.092us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 32.980s | 1.717ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 3.770s | 429.550us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 29.380s | 1.112ms | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1851 | 2042 | 90.65 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 88.36 | 97.56 | 89.93 | 74.17 | 73.81 | 94.48 | 98.52 | 90.06 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 42 failures:
0.i2c_host_mode_toggle.55199579806053601170195460419870616602476009398853247526495117357594900629418
Line 85, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 131864326 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @96539
4.i2c_host_mode_toggle.4308696959164904071489436595419512269983660114691249445697400685213113229380
Line 85, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 193139338 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @30905
... and 14 more failures.
2.i2c_host_stress_all.35084370943332894822822301058294553767491878710930162399126181152977373661840
Line 224, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 48064745609 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2654240
4.i2c_host_stress_all.105689145859928779224542715094561015553186527222561445878071031998145191342646
Line 201, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 37089730894 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @1663058
... and 24 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 27 failures:
0.i2c_target_unexp_stop.63380920699549646702029432704096233452701970778262838784858293912748456548153
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 223818599 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 231 [0xe7])
UVM_INFO @ 223818599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_unexp_stop.93208096305601311747800885794720238121147628554884111571546700621938500640215
Line 78, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 282269457 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 254 [0xfe])
UVM_INFO @ 282269457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 24 more failures.
7.i2c_target_stress_all_with_rand_reset.89667001776784200362224470442046195375931350345082654455687279186169097428680
Line 96, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 165959848 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 79 [0x4f])
UVM_INFO @ 165959848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 25 failures:
3.i2c_target_hrst.14922321877427253251819369531395016108456255568847299415871884378904704042167
Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10079639789 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10079639789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_hrst.61633917266449599171975745037552981444036018352311472882221487296726239772772
Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10015500802 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10015500802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 21 failures:
3.i2c_target_nack_txstretch.76890422980109729662806977984056968960736009597462767847637892236563838892175
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 123953481 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 123953481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_nack_txstretch.70626968386241223494553826258350814481623147507200690225325823426020355581027
Line 78, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 798117655 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 798117655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 18 failures:
1.i2c_target_unexp_stop.43242438581542684557121833411351164960818233544023091198826932084079938154479
Line 78, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 380033182 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 380033182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.105009663148952548315836259988071353748506831050744147909810108976792646092496
Line 78, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 275570338 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 275570338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 16 more failures.
UVM_ERROR (cip_base_vseq.sv:924) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
0.i2c_host_stress_all_with_rand_reset.112350069768288124068379048689257363372961562286572702585756124107463506548321
Line 87, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 446393077 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 446393077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.71919570912041271651116279402283381151942119998915133184175327837402093448455
Line 87, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12015998492 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 12015998492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.93287626582677934597196595741519537442446894365648005939284272757737145977520
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 355205328 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 355205328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.115390873628076382546275273585378489198086789002498319227341026661968761085291
Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1179814103 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1179814103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 9 failures:
3.i2c_host_mode_toggle.49172749854613324947521063989815562059414588231773479156327630548686576988764
Line 87, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 22103525 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
8.i2c_host_mode_toggle.36488889267451550820533436945108210606991359628669304997559900067058079440347
Line 87, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 313861657 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 7 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 7 failures:
0.i2c_target_stretch.24823208627787648786825934917421142918998043558722658158679081557532781378986
Line 78, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10055157699 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10055157699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stretch.112829173138968225818561984223114630301895924177719430414151104088722780017323
Line 78, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10025116633 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10025116633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 6 failures:
16.i2c_target_unexp_stop.79375374238608798204704551220638336392946423290419867319318004933531638993359
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/16.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 85253118 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 85253118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.i2c_target_unexp_stop.6989788846234130324303404259685020258196706286991780475022068211749256946513
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/18.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 281789785 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 281789785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
Job timed out after * minutes has 5 failures:
3.i2c_host_stress_all.17455713129810437968309308484889373744963606897965676599786293783520961413069
Log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
24.i2c_host_stress_all.67439699811387812394768393655221953962959458147939491601358794815920959370985
Log /nightly/runs/scratch/master/i2c-sim-vcs/24.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
... and 2 more failures.
48.i2c_host_perf.62879449250311690623954372858337761724757464573016123861337021696278823686598
Log /nightly/runs/scratch/master/i2c-sim-vcs/48.i2c_host_perf/latest/run.log
Job timed out after 60 minutes
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 4 failures:
2.i2c_host_mode_toggle.27914047966758086916694061421149218036724189705871895488454551148368073378083
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 80573286 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x82af9594, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 80573286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.i2c_host_mode_toggle.9619738490022465853924821012073427501092844483869313338011775293542753577173
Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/11.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 50048241 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xc16ba294, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 50048241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 4 failures:
7.i2c_host_stress_all.53666062800530656143506174541369859563131117334985230145489201402044589541699
Line 138, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 92327930714 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4797606
25.i2c_host_stress_all.51838468334820558654884911583243027287307457531563152363782578498043606317165
Line 157, in log /nightly/runs/scratch/master/i2c-sim-vcs/25.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 21265267675 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @2492614
... and 2 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
Test i2c_target_fifo_watermarks_tx has 2 failures.
0.i2c_target_fifo_watermarks_tx.32413602644527657587693929952199299182790131496052327626160618049452047260066
Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
36.i2c_target_fifo_watermarks_tx.36001980148810998123211202025796350170269397001936033434941896081733245141085
Line 120, in log /nightly/runs/scratch/master/i2c-sim-vcs/36.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_tx_stretch_ctrl has 1 failures.
41.i2c_target_tx_stretch_ctrl.61660612433050950743773610034601005074514520195460365858520642989522540176615
Line 124, in log /nightly/runs/scratch/master/i2c-sim-vcs/41.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (i2c_base_vseq.sv:760) [i2c_target_perf_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == *) has 1 failures:
1.i2c_target_stress_all_with_rand_reset.78413209052867068244002465093223289860304377882827640286485542332112438671123
Line 117, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3090781045 ps: (i2c_base_vseq.sv:760) [uvm_test_top.env.virtual_sequencer.i2c_target_perf_vseq] Check failed (cfg.m_i2c_agent_cfg.rcvd_rd_byte == 0)
UVM_INFO @ 3090781045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:828) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
8.i2c_target_stress_all_with_rand_reset.24537671800562110030937730229772714707092098022606396757306282704869708294450
Line 83, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 703215264 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 703215264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access has 1 failures:
14.i2c_host_mode_toggle.35650767202043933341602719450908318251912816785169226904465729315339757913970
Line 86, in log /nightly/runs/scratch/master/i2c-sim-vcs/14.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.