KEYMGR Simulation Results

Friday April 18 2025 17:34:30 UTC

GitHub Revision: `97d23b4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	35.130s	3.194ms	50	50	100.00
V1	random	keymgr_random	1.060m	2.044ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.500s	130.586us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.370s	9.733us	13	20	65.00
V1	csr_bit_bash	keymgr_csr_bit_bash	19.810s	3.719ms	4	5	80.00
V1	csr_aliasing	keymgr_csr_aliasing	8.460s	253.373us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.020s	50.232us	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.370s	9.733us	13	20	65.00
		keymgr_csr_aliasing	8.460s	253.373us	5	5	100.00
V1		TOTAL			144	155	92.90
V2	cfgen_during_op	keymgr_cfg_regwen	1.592m	2.958ms	50	50	100.00
V2	sideload	keymgr_sideload	32.410s	1.638ms	50	50	100.00
		keymgr_sideload_kmac	42.660s	1.711ms	49	50	98.00
		keymgr_sideload_aes	47.010s	8.701ms	50	50	100.00
		keymgr_sideload_otbn	48.370s	3.428ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	17.920s	1.861ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	8.270s	172.021us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	17.060s	488.659us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	27.660s	980.212us	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	58.430s	3.888ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	19.970s	1.893ms	49	50	98.00
V2	stress_all	keymgr_stress_all	9.090m	69.129ms	50	50	100.00
V2	intr_test	keymgr_intr_test	2.380s	45.989us	50	50	100.00
V2	alert_test	keymgr_alert_test	2.530s	52.243us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.910s	746.578us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.910s	746.578us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.500s	130.586us	5	5	100.00
		keymgr_csr_rw	2.370s	9.733us	13	20	65.00
		keymgr_csr_aliasing	8.460s	253.373us	5	5	100.00
		keymgr_same_csr_outstanding	5.410s	118.946us	13	20	65.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.500s	130.586us	5	5	100.00
		keymgr_csr_rw	2.370s	9.733us	13	20	65.00
		keymgr_csr_aliasing	8.460s	253.373us	5	5	100.00
		keymgr_same_csr_outstanding	5.410s	118.946us	13	20	65.00
V2		TOTAL			730	740	98.65
V2S	sec_cm_additional_check	keymgr_sec_cm	34.910s	2.523ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	34.910s	2.523ms	5	5	100.00
		keymgr_tl_intg_err	7.670s	787.044us	13	20	65.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	6.700s	238.745us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	6.700s	238.745us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	6.700s	238.745us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	6.700s	238.745us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.040s	430.600us	13	20	65.00
V2S	prim_count_check	keymgr_sec_cm	34.910s	2.523ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	34.910s	2.523ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.670s	787.044us	13	20	65.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	6.700s	238.745us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.592m	2.958ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.060m	2.044ms	50	50	100.00
		keymgr_csr_rw	2.370s	9.733us	13	20	65.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.060m	2.044ms	50	50	100.00
		keymgr_csr_rw	2.370s	9.733us	13	20	65.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.060m	2.044ms	50	50	100.00
		keymgr_csr_rw	2.370s	9.733us	13	20	65.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	8.270s	172.021us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	58.430s	3.888ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	58.430s	3.888ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.060m	2.044ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	47.760s	6.550ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	34.910s	2.523ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	34.910s	2.523ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	34.910s	2.523ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	24.670s	4.760ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	8.270s	172.021us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	34.910s	2.523ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	34.910s	2.523ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	34.910s	2.523ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	24.670s	4.760ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	24.670s	4.760ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	34.910s	2.523ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	24.670s	4.760ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	34.910s	2.523ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	24.670s	4.760ms	49	50	98.00
V2S		TOTAL			150	165	90.91
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	25.910s	1.266ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			1053	1110	94.86

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.80	99.10	98.07	98.56	100.00	99.02	98.63	91.21

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 32 failures:

Test keymgr_tl_intg_err has 7 failures.

0.keymgr_tl_intg_err.36869560775336607445871669063506925830634530531150089346032991527463450376593
Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
  UVM_ERROR @   8810852 ps: (keymgr_csr_assert_fpv.sv:466) [ASSERT FAILED] attest_sw_binding_7_rd_A
  UVM_INFO @   8810852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.keymgr_tl_intg_err.72420645263729979042864202139933282620960769148836146576498898700768696500488
Line 83, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
  UVM_ERROR @  16404221 ps: (keymgr_csr_assert_fpv.sv:446) [ASSERT FAILED] attest_sw_binding_3_rd_A
  UVM_INFO @  16404221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test keymgr_shadow_reg_errors_with_csr_rw has 7 failures.

1.keymgr_shadow_reg_errors_with_csr_rw.23845923223785139274639267366402825312167430722299603301904750017190540853998
Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
  UVM_ERROR @   8903361 ps: (keymgr_csr_assert_fpv.sv:391) [ASSERT FAILED] sealing_sw_binding_0_rd_A
  UVM_INFO @   8903361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.keymgr_shadow_reg_errors_with_csr_rw.109457103078965627482439188363255369867664453404707897212502537789512047556408
Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
  UVM_ERROR @  99278112 ps: (keymgr_csr_assert_fpv.sv:421) [ASSERT FAILED] sealing_sw_binding_6_rd_A
  UVM_INFO @  99278112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test keymgr_csr_rw has 7 failures.

3.keymgr_csr_rw.41964463954291334419135764735810395129883741031231934875870612095462361607523
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
  UVM_ERROR @  10537485 ps: (keymgr_csr_assert_fpv.sv:406) [ASSERT FAILED] sealing_sw_binding_3_rd_A
  UVM_INFO @  10537485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.keymgr_csr_rw.102382355006318275647269060916497067703167245545164179142606693911955159862506
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
  UVM_ERROR @  23019820 ps: (keymgr_csr_assert_fpv.sv:411) [ASSERT FAILED] sealing_sw_binding_4_rd_A
  UVM_INFO @  23019820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test keymgr_csr_bit_bash has 1 failures.

3.keymgr_csr_bit_bash.22190515200043723220512153223099310907351236450323150259540178805221188731699
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
  UVM_ERROR @ 873714355 ps: (keymgr_csr_assert_fpv.sv:406) [ASSERT FAILED] sealing_sw_binding_3_rd_A
  UVM_INFO @ 873714355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_same_csr_outstanding has 7 failures.

4.keymgr_same_csr_outstanding.52236501397713938083138043719225220330004804645600446899570290088880743965893
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[5] & 'hffffffff)))'
  UVM_ERROR @  19122727 ps: (keymgr_csr_assert_fpv.sv:391) [ASSERT FAILED] sealing_sw_binding_0_rd_A
  UVM_INFO @  19122727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.keymgr_same_csr_outstanding.16225079823572963634002679968924907534105523624913307532017441925197536979239
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/7.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[6] & 'hffffffff)))'
  UVM_ERROR @ 467293420 ps: (keymgr_csr_assert_fpv.sv:396) [ASSERT FAILED] sealing_sw_binding_1_rd_A
  UVM_INFO @ 467293420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

... and 1 more tests.

UVM_ERROR (cip_base_vseq.sv:924) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test keymgr_stress_all_with_rand_reset has 19 failures.
  - 2.keymgr_stress_all_with_rand_reset.107694662235618730657462896963674481395780144200955881046792922156126722898226
    Line 137, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 154121606 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 154121606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.keymgr_stress_all_with_rand_reset.59575582514065746023910669340633271685107708588470641961193829132424775566452
    Line 653, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 835903899 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 835903899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.
UVM_ERROR (cip_base_scoreboard.sv:349) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 22.keymgr_sync_async_fault_cross.32622271536013351079308907981892783335910566404770922885559491524797757683178
    Line 89, in log /nightly/runs/scratch/master/keymgr-sim-vcs/22.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @   5060366 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   5060366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sideload_kmac has 1 failures.
  - 33.keymgr_sideload_kmac.83332543569441973076954903340936038654174172559593024097502727018909957366135
    Line 91, in log /nightly/runs/scratch/master/keymgr-sim-vcs/33.keymgr_sideload_kmac/latest/run.log
```
  UVM_ERROR @  13192783 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  13192783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_custom_cm has 1 failures.
  - 48.keymgr_custom_cm.104817170086966304163095949720983253112988636819378553309447446976095333308180
    Line 93, in log /nightly/runs/scratch/master/keymgr-sim-vcs/48.keymgr_custom_cm/latest/run.log
```
  UVM_ERROR @  64365186 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  64365186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 5.keymgr_stress_all_with_rand_reset.25439041358096930868028772499486334049958445674772075140196887290467025632633
    Line 211, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 195600716 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 195600716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 14.keymgr_stress_all_with_rand_reset.27565225401992624832676308067771979904197974021661978746040965731107160619700
    Line 614, in log /nightly/runs/scratch/master/keymgr-sim-vcs/14.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1616556459 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1616556459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StDisabled for Attestation Aes has 1 failures:

Test keymgr_lc_disable has 1 failures.

24.keymgr_lc_disable.39213335520060962533740789261322306143702519540376651540767239122012931787615
Line 333, in log /nightly/runs/scratch/master/keymgr-sim-vcs/24.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 192582410 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (13047655404083578724491136412344785094596778410703590691327412199097588965249215802204837380932353440590071022265059807314919209666100815713397453538010339 [0xf91f9c729b3ec1e3938fac33449226c7357a907b77e46539b8bcb55443188cdba7f5da00447802294a8669f260a57659e44bcc48efdc48d2c834b77f29a924e3] vs 13047655404083578724491136412344785094596778410703590691327412199097588965249215802204837380932353440590071022265059807314919209666100815713397453538010339 [0xf91f9c729b3ec1e3938fac33449226c7357a907b77e46539b8bcb55443188cdba7f5da00447802294a8669f260a57659e44bcc48efdc48d2c834b77f29a924e3]) AES key at state StDisabled for Attestation Aes
  UVM_INFO @ 192582410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---