KEYMGR_DPE Simulation Results

Friday April 18 2025 17:34:30 UTC

GitHub Revision: `97d23b4`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	4.578m	51.857ms	48	50	96.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	3.070s	36.149us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	2.980s	26.213us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	13.870s	2.381ms	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	5.880s	914.293us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	3.290s	144.769us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	2.980s	26.213us	20	20	100.00
		keymgr_dpe_csr_aliasing	5.880s	914.293us	5	5	100.00
V1		TOTAL			102	105	97.14
V2	intr_test	keymgr_dpe_intr_test	2.420s	181.643us	50	50	100.00
V2	alert_test	keymgr_dpe_alert_test	2.890s	27.130us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	5.960s	610.061us	20	20	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	5.960s	610.061us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	3.070s	36.149us	5	5	100.00
		keymgr_dpe_csr_rw	2.980s	26.213us	20	20	100.00
		keymgr_dpe_csr_aliasing	5.880s	914.293us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	4.120s	303.666us	19	20	95.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	3.070s	36.149us	5	5	100.00
		keymgr_dpe_csr_rw	2.980s	26.213us	20	20	100.00
		keymgr_dpe_csr_aliasing	5.880s	914.293us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	4.120s	303.666us	19	20	95.00
V2		TOTAL			139	140	99.29
V2S	tl_intg_err	keymgr_dpe_sec_cm	14.030s	888.892us	5	5	100.00
		keymgr_dpe_tl_intg_err	8.030s	265.536us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	5.960s	238.053us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	5.960s	238.053us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	5.960s	238.053us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	5.960s	238.053us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	7.290s	964.239us	20	20	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	14.030s	888.892us	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	14.030s	888.892us	5	5	100.00
V2S		TOTAL			65	65	100.00
		TOTAL			306	310	98.71

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
77.07	97.57	90.70	63.14	76.92	94.91	98.57	17.68

Failure Buckets

UVM_ERROR (keymgr_dpe_scoreboard.sv:565) scoreboard [scoreboard] After a disable kmac sideload key was not presevedexp * vs. act * has 2 failures:

Test keymgr_dpe_smoke has 2 failures.

45.keymgr_dpe_smoke.99581013899763008821172305523208967898946687402983800264312376675429424033702
Line 2801, in log /nightly/runs/scratch/master/keymgr_dpe-sim-vcs/45.keymgr_dpe_smoke/latest/run.log

  UVM_ERROR @ 626719444 ps: (keymgr_dpe_scoreboard.sv:565) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] After a disable kmac sideload key was not presevedexp 'h45e1fc6454ec86a90973a4a5442770b23d5f1ee2c3fcb49f34eb96256858a202c025c8499e9234075af3fb81b5aa0815633f5d989e822532f0fd38ce56f62bfb vs. act 'h0
  UVM_INFO @ 626719444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.keymgr_dpe_smoke.88620876100554507311449993200263377595546182527782492666185883894885878531613
Line 3028, in log /nightly/runs/scratch/master/keymgr_dpe-sim-vcs/48.keymgr_dpe_smoke/latest/run.log

  UVM_ERROR @ 373439960 ps: (keymgr_dpe_scoreboard.sv:565) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] After a disable kmac sideload key was not presevedexp 'h21a6fa4e0ec3c532e613e08582336a691dfbfa9240b4fe0608b784b1c8cb2334459bcf83a3e29b6a906c3ca8eebdbbae1a424c960378115fdc67af28ec0aaddb vs. act 'h0
  UVM_INFO @ 373439960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:294) [keymgr_dpe_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test keymgr_dpe_same_csr_outstanding has 1 failures.
  - 4.keymgr_dpe_same_csr_outstanding.8405684175707295006649954118844127077342305693629403652019600392859938190136
    Line 75, in log /nightly/runs/scratch/master/keymgr_dpe-sim-vcs/4.keymgr_dpe_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @   2236262 ps: (cip_base_vseq.sv:294) [uvm_test_top.env.virtual_sequencer.keymgr_dpe_common_vseq] Check failed masked_data == exp_data (256 [0x100] vs 0 [0x0]) addr 0x9092f0d0 read out mismatch
  UVM_INFO @   2236262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: keymgr_dpe_reg_block.debug reset value: * has 1 failures:
- Test keymgr_dpe_csr_mem_rw_with_rand_reset has 1 failures.
  - 19.keymgr_dpe_csr_mem_rw_with_rand_reset.46204376612657717718562057281689030484982814775387444529263532524255306659798
    Line 83, in log /nightly/runs/scratch/master/keymgr_dpe-sim-vcs/19.keymgr_dpe_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  99415452 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (256 [0x100] vs 0 [0x0]) Regname: keymgr_dpe_reg_block.debug reset value: 0x0
  UVM_INFO @  99415452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```