KMAC/MASKED Simulation Results

Friday April 18 2025 17:34:30 UTC

GitHub Revision: 97d23b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.418m	37.846ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.810s	28.387us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.670s	33.985us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.080s	5.643ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.590s	2.158ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.880s	154.463us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.670s	33.985us	20	20	100.00
		kmac_csr_aliasing	9.590s	2.158ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.310s	12.002us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.920s	142.130us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	57.529m	188.026ms	50	50	100.00
V2	burst_write	kmac_burst_write	23.358m	123.246ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	37.973m	99.576ms	5	5	100.00
		kmac_test_vectors_sha3_256	35.407m	335.821ms	5	5	100.00
		kmac_test_vectors_sha3_384	26.187m	372.787ms	5	5	100.00
		kmac_test_vectors_sha3_512	17.430m	33.320ms	5	5	100.00
		kmac_test_vectors_shake_128	30.897m	24.693ms	5	5	100.00
		kmac_test_vectors_shake_256	34.273m	426.655ms	5	5	100.00
		kmac_test_vectors_kmac	4.330s	176.205us	5	5	100.00
		kmac_test_vectors_kmac_xof	5.190s	767.806us	5	5	100.00
V2	sideload	kmac_sideload	8.753m	83.769ms	50	50	100.00
V2	app	kmac_app	5.928m	6.472ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.508m	69.558ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.778m	156.098ms	50	50	100.00
V2	error	kmac_error	7.805m	27.786ms	50	50	100.00
V2	key_error	kmac_key_error	18.100s	5.619ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	13.230s	1.356ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	40.660s	13.389ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	43.220s	8.508ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	57.570s	17.044ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.052m	3.984ms	50	50	100.00
V2	stress_all	kmac_stress_all	35.041m	975.007ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.580s	33.842us	50	50	100.00
V2	alert_test	kmac_alert_test	2.390s	180.142us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.190s	56.223us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.190s	56.223us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.810s	28.387us	5	5	100.00
		kmac_csr_rw	2.670s	33.985us	20	20	100.00
		kmac_csr_aliasing	9.590s	2.158ms	5	5	100.00
		kmac_same_csr_outstanding	4.010s	124.971us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.810s	28.387us	5	5	100.00
		kmac_csr_rw	2.670s	33.985us	20	20	100.00
		kmac_csr_aliasing	9.590s	2.158ms	5	5	100.00
		kmac_same_csr_outstanding	4.010s	124.971us	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.200s	907.838us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.200s	907.838us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.200s	907.838us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.200s	907.838us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.740s	342.285us	13	20	65.00
V2S	tl_intg_err	kmac_sec_cm	1.384m	26.656ms	5	5	100.00
		kmac_tl_intg_err	4.590s	196.280us	10	20	50.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.590s	196.280us	10	20	50.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.052m	3.984ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.418m	37.846ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.753m	83.769ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.200s	907.838us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.384m	26.656ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.384m	26.656ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.384m	26.656ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.418m	37.846ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.052m	3.984ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.384m	26.656ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.099m	20.492ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.418m	37.846ms	50	50	100.00
V2S		TOTAL			58	75	77.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	5.629m	4.666ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			918	940	97.66

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.57	99.09	94.47	99.89	81.69	97.05	98.90	97.86

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 16 failures:
  • Test kmac_tl_intg_err has 10 failures.

    • 2.kmac_tl_intg_err.74955272558512324132747226373725633364027822358434859173820170987849107706236
      Line 93, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[46] & 'hffffffff)))'
        UVM_ERROR @  57132243 ps: (kmac_csr_assert_fpv.sv:527) [ASSERT FAILED] prefix_7_rd_A
        UVM_INFO @  57132243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.kmac_tl_intg_err.81474850342427873406991354347667049565023709157154217388588532918120202786115
      Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
        UVM_ERROR @  10345147 ps: (kmac_csr_assert_fpv.sv:492) [ASSERT FAILED] prefix_0_rd_A
        UVM_INFO @  10345147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

  • Test kmac_shadow_reg_errors_with_csr_rw has 6 failures.

    • 4.kmac_shadow_reg_errors_with_csr_rw.105755217570939601726788095821070891524021527611167090259093868964591155732506
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
        UVM_ERROR @  37069074 ps: (kmac_csr_assert_fpv.sv:487) [ASSERT FAILED] entropy_period_rd_A
        UVM_INFO @  37069074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.kmac_shadow_reg_errors_with_csr_rw.28590232641499362254639364939701948929913165090991774066959387070475578818046
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
        UVM_ERROR @  30015511 ps: (kmac_csr_assert_fpv.sv:507) [ASSERT FAILED] prefix_3_rd_A
        UVM_INFO @  30015511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 4 more failures.

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
  • Test kmac_stress_all_with_rand_reset has 5 failures.

    • 0.kmac_stress_all_with_rand_reset.41411254028687811746959832627409522793834921994253003409707575369592037166542
      Line 186, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5249839182 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 5249839182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.kmac_stress_all_with_rand_reset.31812018187351922592729986078171592993212412094933336471671696191997117685345
      Line 179, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6290475485 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 6290475485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 13.kmac_shadow_reg_errors_with_csr_rw.24378000889741572999105209350452908634289153711567895584753216449495102454625
      Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @ 242109776 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (217708855 [0xcf9f937] vs 243137743 [0xe7dfccf]) Regname: kmac_reg_block.prefix_10 reset value: 0x0
        UVM_INFO @ 242109776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---