KMAC/UNMASKED Simulation Results

Friday April 18 2025 17:34:30 UTC

GitHub Revision: `97d23b4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.209m	4.312ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.670s	37.814us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.710s	27.831us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.280s	365.653us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.100s	783.873us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.500s	108.120us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.710s	27.831us	20	20	100.00
		kmac_csr_aliasing	9.100s	783.873us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.330s	15.701us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.560s	31.014us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	49.824m	921.890ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.309m	24.835ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	29.779m	123.629ms	5	5	100.00
		kmac_test_vectors_sha3_256	30.811m	183.165ms	5	5	100.00
		kmac_test_vectors_sha3_384	22.003m	374.343ms	5	5	100.00
		kmac_test_vectors_sha3_512	15.634m	192.512ms	5	5	100.00
		kmac_test_vectors_shake_128	3.102m	9.936ms	5	5	100.00
		kmac_test_vectors_shake_256	22.268m	32.815ms	5	5	100.00
		kmac_test_vectors_kmac	4.340s	111.669us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.510s	89.573us	5	5	100.00
V2	sideload	kmac_sideload	6.634m	20.455ms	50	50	100.00
V2	app	kmac_app	5.494m	17.767ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.487m	64.859ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.377m	15.768ms	50	50	100.00
V2	error	kmac_error	6.473m	30.528ms	48	50	96.00
V2	key_error	kmac_key_error	14.930s	6.314ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.630m	10.059ms	39	50	78.00
V2	edn_timeout_error	kmac_edn_timeout_error	45.760s	9.342ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	50.590s	19.190ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	53.870s	25.297ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	39.730s	3.201ms	50	50	100.00
V2	stress_all	kmac_stress_all	32.618m	94.496ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.430s	45.146us	50	50	100.00
V2	alert_test	kmac_alert_test	2.240s	21.972us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.340s	142.944us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.340s	142.944us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.670s	37.814us	5	5	100.00
		kmac_csr_rw	2.710s	27.831us	20	20	100.00
		kmac_csr_aliasing	9.100s	783.873us	5	5	100.00
		kmac_same_csr_outstanding	3.890s	1.532ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.670s	37.814us	5	5	100.00
		kmac_csr_rw	2.710s	27.831us	20	20	100.00
		kmac_csr_aliasing	9.100s	783.873us	5	5	100.00
		kmac_same_csr_outstanding	3.890s	1.532ms	20	20	100.00
V2		TOTAL			727	740	98.24
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.640s	253.670us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.640s	253.670us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.640s	253.670us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.640s	253.670us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.790s	197.678us	10	20	50.00
V2S	tl_intg_err	kmac_sec_cm	1.193m	11.638ms	5	5	100.00
		kmac_tl_intg_err	5.490s	282.737us	13	20	65.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.490s	282.737us	13	20	65.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	39.730s	3.201ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.209m	4.312ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.634m	20.455ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.640s	253.670us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.193m	11.638ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.193m	11.638ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.193m	11.638ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.209m	4.312ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	39.730s	3.201ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.193m	11.638ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.936m	10.475ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.209m	4.312ms	50	50	100.00
V2S		TOTAL			58	75	77.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.325m	26.010ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			903	940	96.06

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.62	97.18	94.38	100.00	72.73	95.93	99.02	96.13

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 17 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 10 failures.

0.kmac_shadow_reg_errors_with_csr_rw.24496966803251653057125570671517805810694177146973271744214015917045184038158
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
  UVM_ERROR @  16236491 ps: (kmac_csr_assert_fpv.sv:497) [ASSERT FAILED] prefix_1_rd_A
  UVM_INFO @  16236491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.kmac_shadow_reg_errors_with_csr_rw.59469016808870153111088775607248659124547424085379758490151022720618308450757
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
  UVM_ERROR @   4876372 ps: (kmac_csr_assert_fpv.sv:492) [ASSERT FAILED] prefix_0_rd_A
  UVM_INFO @   4876372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test kmac_tl_intg_err has 7 failures.

0.kmac_tl_intg_err.110028526688690892777228724265744744632659625308829024664747743210950835137813
Line 90, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
  UVM_ERROR @  36504336 ps: (kmac_csr_assert_fpv.sv:492) [ASSERT FAILED] prefix_0_rd_A
  UVM_INFO @  36504336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.kmac_tl_intg_err.109599879194000712369820730908194810660897699339163666232994303980421460226003
Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
  UVM_ERROR @  20600391 ps: (kmac_csr_assert_fpv.sv:487) [ASSERT FAILED] entropy_period_rd_A
  UVM_INFO @  20600391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 5 failures:
- Test kmac_stress_all_with_rand_reset has 5 failures.
  - 0.kmac_stress_all_with_rand_reset.33467773570129901967076975453023682021729626968300745254846691139472335404395
    Line 111, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 11302847197 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 11302847197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.kmac_stress_all_with_rand_reset.52514452907274941660465926590612128555652616283125680094497095252286697497825
    Line 180, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6408106484 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 6408106484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 4 failures:
- Test kmac_sideload_invalid has 4 failures.
  - 3.kmac_sideload_invalid.38723498226825512026785159228929052638598665405845422539168187850785354174196
    Line 74, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10016131239 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6895d000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 10016131239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.kmac_sideload_invalid.94387159152613870644428773974283060279615826809328911024421353985648478917649
    Line 74, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/6.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10015520813 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4cc2e000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 10015520813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 4.kmac_sideload_invalid.76025207933441813618425510438000995573266093311004538673035366456731274062355
    Line 78, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10064228924 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5348d000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
  UVM_INFO @ 10064228924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 44.kmac_sideload_invalid.20309220004288489259425834939376386139762517817217892651256560035531121467812
    Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/44.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10057778503 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x79d99000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
  UVM_INFO @ 10057778503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:924) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 4.kmac_stress_all_with_rand_reset.104805482965062585711826444216928262708778125817161484563376381423451743037837
    Line 132, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14081029814 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14081029814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.kmac_stress_all_with_rand_reset.57773267258862954158456016962933870192587695375665514046597260430317262898449
    Line 105, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2232153007 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2232153007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_error has 2 failures.
  - 9.kmac_error.80697831976877933877603373412788158811039536177186444848431503870713592579153
    Line 205, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/9.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 28.kmac_error.28789784245609187768347604920880181918645679238800954643040682462629075113978
    Line 238, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/28.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 0.kmac_sideload_invalid.19460014717389529139098422543024021442889425570184821101628386309563824842623
    Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10059140736 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x58e09000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
  UVM_INFO @ 10059140736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 8.kmac_sideload_invalid.98358196041020150388649382137652111966833128656935942398445459688789516842441
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/8.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10033581138 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x50d6e000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10033581138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 28.kmac_sideload_invalid.48639537768711824350778053497626483273003596216677971306314770597713271334939
    Line 84, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/28.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10524305046 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd99be000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
  UVM_INFO @ 10524305046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 34.kmac_sideload_invalid.57723786288628139610438787593234719716378138361283258379482930352333685850161
    Line 90, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/34.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10383265718 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6ac4b000, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
  UVM_INFO @ 10383265718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 37.kmac_sideload_invalid.77941548649814111125282039404701947591737716357951094239336013467041349758472
    Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/37.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10284269825 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x36cb4000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
  UVM_INFO @ 10284269825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```