OTBN Simulation Results

Friday April 18 2025 17:34:30 UTC

GitHub Revision: `97d23b4`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	15.000s	110.962us	1	1	100.00
V1	single_binary	otbn_single	3.467m	1.957ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	19.000s	28.419us	5	5	100.00
V1	csr_rw	otbn_csr_rw	12.000s	27.259us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	68.092us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	8.000s	15.451us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	14.000s	47.999us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	12.000s	27.259us	20	20	100.00
		otbn_csr_aliasing	8.000s	15.451us	5	5	100.00
V1	mem_walk	otbn_mem_walk	1.017m	2.489ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	40.000s	164.991us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	48.000s	258.450us	10	10	100.00
V2	multi_error	otbn_multi_err	56.000s	173.708us	1	1	100.00
V2	back_to_back	otbn_multi	2.717m	604.986us	10	10	100.00
V2	stress_all	otbn_stress_all	9.200m	2.957ms	10	10	100.00
V2	lc_escalation	otbn_escalate	28.000s	77.578us	60	60	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	10.000s	13.269us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	18.000s	80.229us	10	10	100.00
V2	alert_test	otbn_alert_test	14.000s	36.061us	50	50	100.00
V2	intr_test	otbn_intr_test	35.000s	10.554us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	46.000s	87.906us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	46.000s	87.906us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	19.000s	28.419us	5	5	100.00
		otbn_csr_rw	12.000s	27.259us	20	20	100.00
		otbn_csr_aliasing	8.000s	15.451us	5	5	100.00
		otbn_same_csr_outstanding	15.000s	54.146us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	19.000s	28.419us	5	5	100.00
		otbn_csr_rw	12.000s	27.259us	20	20	100.00
		otbn_csr_aliasing	8.000s	15.451us	5	5	100.00
		otbn_same_csr_outstanding	15.000s	54.146us	20	20	100.00
V2		TOTAL			246	246	100.00
V2S	mem_integrity	otbn_imem_err	14.000s	88.460us	10	10	100.00
		otbn_dmem_err	19.000s	51.673us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	15.000s	27.831us	5	5	100.00
		otbn_controller_ispr_rdata_err	17.000s	92.906us	5	5	100.00
		otbn_mac_bignum_acc_err	15.000s	227.229us	5	5	100.00
		otbn_urnd_err	7.000s	62.429us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	10.000s	13.003us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	13.053us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	14.000s	47.373us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	3.967m	1.125ms	2	5	40.00
		otbn_tl_intg_err	51.000s	202.088us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.033m	321.177us	15	20	75.00
V2S	prim_fsm_check	otbn_sec_cm	3.967m	1.125ms	2	5	40.00
V2S	prim_count_check	otbn_sec_cm	3.967m	1.125ms	2	5	40.00
V2S	sec_cm_mem_scramble	otbn_smoke	15.000s	110.962us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	19.000s	51.673us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	14.000s	88.460us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	51.000s	202.088us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	28.000s	77.578us	60	60	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	14.000s	88.460us	10	10	100.00
		otbn_dmem_err	19.000s	51.673us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	13.269us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	13.003us	5	5	100.00
		otbn_sec_cm	3.967m	1.125ms	2	5	40.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	3.967m	1.125ms	2	5	40.00
V2S	sec_cm_scramble_key_sideload	otbn_single	3.467m	1.957ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	14.000s	88.460us	10	10	100.00
		otbn_dmem_err	19.000s	51.673us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	13.269us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	13.003us	5	5	100.00
		otbn_sec_cm	3.967m	1.125ms	2	5	40.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	3.967m	1.125ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	28.000s	77.578us	60	60	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	14.000s	88.460us	10	10	100.00
		otbn_dmem_err	19.000s	51.673us	15	15	100.00
		otbn_zero_state_err_urnd	10.000s	13.269us	5	5	100.00
		otbn_illegal_mem_acc	10.000s	13.003us	5	5	100.00
		otbn_sec_cm	3.967m	1.125ms	2	5	40.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	3.967m	1.125ms	2	5	40.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	3.467m	1.957ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	15.000s	32.562us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	79.177us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.317m	2.909ms	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.317m	2.909ms	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	16.000s	51.858us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	3.967m	1.125ms	2	5	40.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	3.967m	1.125ms	2	5	40.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	39.000s	112.944us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	3.967m	1.125ms	2	5	40.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	3.967m	1.125ms	2	5	40.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	24.491us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	24.491us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	15.000s	16.714us	4	7	57.14
V2S	sec_cm_data_mem_sec_wipe	otbn_single	3.467m	1.957ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	3.467m	1.957ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	3.467m	1.957ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	2.717m	604.986us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	3.467m	1.957ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	3.467m	1.957ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	13.000s	33.188us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	3.467m	1.957ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	3.967m	1.125ms	2	5	40.00
V2S		TOTAL			152	163	93.25
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	5.617m	9.816ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			565	585	96.58

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.06	99.61	95.58	99.72	93.07	93.21	100.00	97.72	100.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:925) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test otbn_stress_all_with_rand_reset has 8 failures.
  - 0.otbn_stress_all_with_rand_reset.48854554429292771784410407059571661832369546070959568511473133929413916571898
    Line 161, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 209782988 ps: (cip_base_vseq.sv:925) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 209782988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.otbn_stress_all_with_rand_reset.7682657972273960844161472555993338593512715691361257762716178186821193220597
    Line 293, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9815850681 ps: (cip_base_vseq.sv:925) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9815850681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 4 failures:
- Test otbn_passthru_mem_tl_intg_err has 4 failures.
  - 3.otbn_passthru_mem_tl_intg_err.22600817876672415611882509529421887091435694160850604845971270592709642654878
    Line 97, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @  54279558 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @  54279558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 11.otbn_passthru_mem_tl_intg_err.22224871698353400648678417636564158592135741904027474857240857138422938101648
    Line 92, in log /nightly/runs/scratch/master/otbn-sim-xcelium/11.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @  63799896 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @  63799896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 3 failures:

Test otbn_sec_wipe_err has 3 failures.

0.otbn_sec_wipe_err.93609020455861968611966243288841104661740212975669445480955439700934183892589
Line 111, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 16713587 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  16713587 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  16713587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.otbn_sec_wipe_err.42055230880735014332803930635299551604370933133014657857740349702009462801410
Line 112, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 20938341 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  20938341 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  20938341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 3 failures:

Test otbn_sec_cm has 3 failures.

0.otbn_sec_cm.108211133944349978071819455140593462362459728400547919492115559142773104619362
Line 93, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 30945511 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 30945511 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @  30945511 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @  30945511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.otbn_sec_cm.92792738854230324115542190456504288556926254961043199363614020618563415786075
Line 88, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 33238308 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 33238308 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @  33238308 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @  33238308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.19151177453084380919754550419106470220010876147179547026717517789753793451622
    Line 191, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 539045709 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 539045709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_passthru_mem_tl_intg_err has 1 failures.
  - 17.otbn_passthru_mem_tl_intg_err.75646633664126784110710062575886793612372358141311975143052253521074207858413
    Line 167, in log /nightly/runs/scratch/master/otbn-sim-xcelium/17.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 299249606 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @ 299249606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```