ROM_CTRL/32KB Simulation Results

Friday April 18 2025 17:34:30 UTC

GitHub Revision: 97d23b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	11.900s	2.207ms	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	9.370s	310.984us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	8.050s	4.989ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	8.790s	1.785ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	7.600s	557.869us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.900s	617.369us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	8.050s	4.989ms	20	20	100.00
		rom_ctrl_csr_aliasing	7.600s	557.869us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	9.590s	2.016ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	7.060s	280.491us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	7.490s	413.082us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	30.670s	7.981ms	19	20	95.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	13.410s	1.084ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	8.110s	164.718us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	12.570s	538.118us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	12.570s	538.118us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	9.370s	310.984us	5	5	100.00
		rom_ctrl_csr_rw	8.050s	4.989ms	20	20	100.00
		rom_ctrl_csr_aliasing	7.600s	557.869us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.610s	175.614us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	9.370s	310.984us	5	5	100.00
		rom_ctrl_csr_rw	8.050s	4.989ms	20	20	100.00
		rom_ctrl_csr_aliasing	7.600s	557.869us	5	5	100.00
		rom_ctrl_same_csr_outstanding	9.610s	175.614us	20	20	100.00
V2		TOTAL			113	114	99.12
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.260m	8.458ms	18	20	90.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	32.820s	878.697us	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.333m	3.149ms	5	5	100.00
		rom_ctrl_tl_intg_err	59.870s	3.732ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.333m	3.149ms	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.333m	3.149ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.260m	8.458ms	18	20	90.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.260m	8.458ms	18	20	90.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.260m	8.458ms	18	20	90.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.260m	8.458ms	18	20	90.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.260m	8.458ms	18	20	90.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.333m	3.149ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.333m	3.149ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	11.900s	2.207ms	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	11.900s	2.207ms	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	11.900s	2.207ms	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	59.870s	3.732ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.260m	8.458ms	18	20	90.00
		rom_ctrl_kmac_err_chk	13.410s	1.084ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.260m	8.458ms	18	20	90.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.260m	8.458ms	18	20	90.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.260m	8.458ms	18	20	90.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	32.820s	878.697us	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.333m	3.149ms	5	5	100.00
V2S		TOTAL			63	65	96.92
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	10.693m	5.907ms	19	20	95.00
V3		TOTAL			19	20	95.00
		TOTAL			262	266	98.50

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	100.00	99.41	100.00	100.00	100.00	98.97	99.05

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:691) virtual_sequencer [rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire has 1 failures:

  • Test rom_ctrl_stress_all has 1 failures.

    • 2.rom_ctrl_stress_all.29358767768261755950571609947219199464731377845297153987575963579819492915345
      Line 80, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 1570545010 ps: (cip_base_vseq.sv:691) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.rom_ctrl_kmac_err_chk_vseq] expect alert:fatal to fire
        UVM_INFO @ 1570545010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(counter_lnt -> kmac_rom_vld_o)' has 1 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 12.rom_ctrl_corrupt_sig_fatal_chk.74151675159708943616532526344342886273233203187985457741053366831187510237178
      Line 99, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/12.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

            Offending '(counter_lnt -> kmac_rom_vld_o)'
        UVM_ERROR @ 5034730409 ps: (rom_ctrl_fsm.sv:317) [ASSERT FAILED] CounterLntImpliesKmacRomVldO_A
        UVM_INFO @ 5034730409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rom_ctrl_scoreboard.sv:290) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rom_ctrl_regs_reg_block.fatal_alert_cause has 1 failures:

  • Test rom_ctrl_stress_all_with_rand_reset has 1 failures.

    • 15.rom_ctrl_stress_all_with_rand_reset.105337138501769264186967693562566709749416940110541366499419232170869397292999
      Line 104, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/15.rom_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1433472910 ps: (rom_ctrl_scoreboard.sv:290) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: rom_ctrl_regs_reg_block.fatal_alert_cause
        UVM_INFO @ 1433472910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:305) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:

  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 17.rom_ctrl_corrupt_sig_fatal_chk.903864931833165137642610909340210242129782316552848771849448897615827598584
      Line 89, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/17.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 2690170651 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:305) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 2690170651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---