RV_TIMER Simulation Results

Friday April 18 2025 17:34:30 UTC

GitHub Revision: 97d23b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	35.965m	155.067ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	2.110s	30.735us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.120s	47.577us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	4.730s	314.103us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.200s	24.845us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	3.150s	59.856us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.120s	47.577us	20	20	100.00
		rv_timer_csr_aliasing	2.200s	24.845us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	17.447m	379.710ms	50	50	100.00
V2	disabled	rv_timer_disabled	6.610m	205.898ms	46	50	92.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	24.478m	4.194s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	24.478m	4.194s	50	50	100.00
V2	stress	rv_timer_stress_all	1.450h	3.530s	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.120s	18.145us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	4.730s	159.658us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	4.730s	159.658us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	2.110s	30.735us	5	5	100.00
		rv_timer_csr_rw	2.120s	47.577us	20	20	100.00
		rv_timer_csr_aliasing	2.200s	24.845us	5	5	100.00
		rv_timer_same_csr_outstanding	2.360s	38.297us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	2.110s	30.735us	5	5	100.00
		rv_timer_csr_rw	2.120s	47.577us	20	20	100.00
		rv_timer_csr_aliasing	2.200s	24.845us	5	5	100.00
		rv_timer_same_csr_outstanding	2.360s	38.297us	20	20	100.00
V2		TOTAL			286	290	98.62
V2S	tl_intg_err	rv_timer_sec_cm	2.500s	364.340us	5	5	100.00
		rv_timer_tl_intg_err	3.080s	128.361us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	3.080s	128.361us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.273m	24.204ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			579	620	93.39

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.19	99.65	99.08	92.06	--	99.13	99.68	99.54

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:924) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
  • Test rv_timer_stress_all_with_rand_reset has 35 failures.

    • 1.rv_timer_stress_all_with_rand_reset.42017773780678603381625088987024916428952278406285234675877555020090896683039
      Line 72, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 538706434 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 538706434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.rv_timer_stress_all_with_rand_reset.36355212269260316391583134794859807241752105040317363340291107804514784284845
      Line 72, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/4.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 147530242 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 147530242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 33 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
  • Test rv_timer_disabled has 4 failures.

    • 4.rv_timer_disabled.40310356584947657895199499739654272813711099450915211693941126827090900596367
      Line 72, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/4.rv_timer_disabled/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 28.rv_timer_disabled.101674128573391731868545240539985452350123649210716528376800955250125853728678
      Line 73, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/28.rv_timer_disabled/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_vseq.sv:828) [rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
  • Test rv_timer_stress_all_with_rand_reset has 2 failures.

    • 0.rv_timer_stress_all_with_rand_reset.18502646158778353904885742239747227573230654109772711448508544569669800832009
      Line 131, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4820234482 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 4820234482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 29.rv_timer_stress_all_with_rand_reset.5731699487490566908885540222831455090904266646394990905357678879050766941772
      Line 152, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/29.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3919544360 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 3919544360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---