SPI_DEVICE/1R1W Simulation Results

Friday April 18 2025 17:34:30 UTC

GitHub Revision: `97d23b4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	12.071m	1.500s	49	50	98.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.480s	157.440us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.520s	90.129us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	29.160s	33.495ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	23.250s	1.254ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.800s	53.981us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.520s	90.129us	20	20	100.00
		spi_device_csr_aliasing	23.250s	1.254ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.950s	21.819us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.320s	65.265us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	csb_read	spi_device_csb_read	2.630s	106.772us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.600s	1.203us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.990s	1.397us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	12.010s	670.028us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	12.010s	670.028us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	25.020s	45.609ms	50	50	100.00
		spi_device_tpm_sts_read	2.750s	92.567us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	41.250s	19.665ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	30.810s	23.179ms	50	50	100.00
		spi_device_flash_all	6.291m	230.681ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	25.370s	26.440ms	50	50	100.00
		spi_device_flash_all	6.291m	230.681ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	25.370s	26.440ms	50	50	100.00
		spi_device_flash_all	6.291m	230.681ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.291m	230.681ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	29.350s	6.534ms	50	50	100.00
		spi_device_flash_all	6.291m	230.681ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	29.350s	6.534ms	50	50	100.00
		spi_device_flash_all	6.291m	230.681ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	29.350s	6.534ms	50	50	100.00
		spi_device_flash_all	6.291m	230.681ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	29.350s	6.534ms	50	50	100.00
		spi_device_flash_all	6.291m	230.681ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	29.350s	6.534ms	50	50	100.00
		spi_device_flash_all	6.291m	230.681ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	42.080s	136.691ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.719m	28.194ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.719m	28.194ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.719m	28.194ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	48.090s	14.603ms	50	50	100.00
		spi_device_read_buffer_direct	17.160s	7.437ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.719m	28.194ms	50	50	100.00
		spi_device_flash_all	6.291m	230.681ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.291m	230.681ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.291m	230.681ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	23.360s	30.438ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	23.360s	30.438ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	12.071m	1.500s	49	50	98.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.662m	268.671ms	50	50	100.00
V2	stress_all	spi_device_stress_all	20.767m	164.720ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.550s	54.308us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.440s	10.809us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.810s	226.352us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.810s	226.352us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.480s	157.440us	5	5	100.00
		spi_device_csr_rw	3.520s	90.129us	20	20	100.00
		spi_device_csr_aliasing	23.250s	1.254ms	5	5	100.00
		spi_device_same_csr_outstanding	5.510s	168.271us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.480s	157.440us	5	5	100.00
		spi_device_csr_rw	3.520s	90.129us	20	20	100.00
		spi_device_csr_aliasing	23.250s	1.254ms	5	5	100.00
		spi_device_same_csr_outstanding	5.510s	168.271us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	2.760s	967.562us	5	5	100.00
		spi_device_tl_intg_err	19.320s	1.072ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	19.320s	1.072ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.199m	348.728ms	50	50	100.00
		TOTAL			1129	1151	98.09

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.44	98.98	96.23	83.25	89.36	98.37	95.66	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.80122669987128623823733767379722375725132819505772495906018921110372463589705
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1248523 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[76])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1248523 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1248523 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[972])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.21968095676611586708691044467362962007255776062864624967193790285828056990917
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2551931 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[29])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2551931 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2551931 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[925])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.8462014235110035490850837905692032558174623394260872139737557276736328332675
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @    766367 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    766367 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
  UVM_ERROR @    822367 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2496d5 [1001001001011011010101] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
  UVM_ERROR @    822367 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x2496d5 [1001001001011011010101] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_and_tpm has 1 failures.
  - 35.spi_device_flash_and_tpm.35163495637205893460914122543474855340262956080270554892346882236442518125202
    Line 97, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```