SPI_HOST Simulation Results

Friday April 18 2025 17:34:30 UTC

GitHub Revision: 97d23b4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	8.900m	173.095ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	6.000s	17.750us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	6.000s	20.526us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	7.000s	193.586us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	6.000s	20.053us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	6.000s	37.617us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	6.000s	20.526us	20	20	100.00
		spi_host_csr_aliasing	6.000s	20.053us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	6.000s	19.131us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	42.721us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	7.000s	32.769us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	1.167m	1.787ms	50	50	100.00
		spi_host_error_cmd	6.000s	60.036us	50	50	100.00
		spi_host_event	13.900m	27.475ms	50	50	100.00
V2	clock_rate	spi_host_speed	27.000s	1.565ms	50	50	100.00
V2	speed	spi_host_speed	27.000s	1.565ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	27.000s	1.565ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	3.733m	7.827ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	6.000s	1.068ms	50	50	100.00
V2	cpol_cpha	spi_host_speed	27.000s	1.565ms	50	50	100.00
V2	full_cycle	spi_host_speed	27.000s	1.565ms	50	50	100.00
V2	duplex	spi_host_smoke	8.900m	173.095ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	8.900m	173.095ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.667m	14.875ms	50	50	100.00
V2	spien	spi_host_spien	5.683m	65.422ms	50	50	100.00
V2	stall	spi_host_status_stall	5.633m	20.864ms	47	50	94.00
V2	Idlecsbactive	spi_host_idlecsbactive	26.000s	4.079ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	1.167m	1.787ms	50	50	100.00
V2	alert_test	spi_host_alert_test	5.000s	18.767us	50	50	100.00
V2	intr_test	spi_host_intr_test	6.000s	45.433us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	8.000s	544.884us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	8.000s	544.884us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	6.000s	17.750us	5	5	100.00
		spi_host_csr_rw	6.000s	20.526us	20	20	100.00
		spi_host_csr_aliasing	6.000s	20.053us	5	5	100.00
		spi_host_same_csr_outstanding	6.000s	102.820us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	6.000s	17.750us	5	5	100.00
		spi_host_csr_rw	6.000s	20.526us	20	20	100.00
		spi_host_csr_aliasing	6.000s	20.053us	5	5	100.00
		spi_host_same_csr_outstanding	6.000s	102.820us	20	20	100.00
V2		TOTAL			687	690	99.57
V2S	tl_intg_err	spi_host_tl_intg_err	6.000s	63.898us	20	20	100.00
		spi_host_sec_cm	5.000s	356.257us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	6.000s	63.898us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	47.917m	100.001ms	2	10	20.00
		TOTAL			829	840	98.69

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.27	96.74	93.21	98.69	94.51	88.02	100.00	96.86	91.56

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 8 failures:

  • Test spi_host_upper_range_clkdiv has 8 failures.

    • 0.spi_host_upper_range_clkdiv.111108790075516835247460910752842114622644546117645859165305844871558625327959
      Line 112, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100003192186 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xc2aceb14, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100003192186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.spi_host_upper_range_clkdiv.32438351672907785568209496282497673270380905304949121773298010033138504386597
      Line 151, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100004066566 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x9f21b014, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100004066566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 6 more failures.

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=89) has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 21.spi_host_status_stall.107596797565402074882729025615450584318138998978625439949311926432119954605268
      Line 752, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/21.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 10159217607 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xbc9d0394, Comparison=CompareOpEq, exp_data=0x1, call_count=89)
        UVM_INFO @ 10159217607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=166) has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 45.spi_host_status_stall.35521040054684693545916348019382493970395687652538241688561406323989181926613
      Line 843, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/45.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 16775462336 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x6d439094, Comparison=CompareOpEq, exp_data=0x0, call_count=166)
        UVM_INFO @ 16775462336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=80) has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 47.spi_host_status_stall.24679575113122932080041282398349580263971440755261176460109809699877324094824
      Line 709, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/47.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 20863578602 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x8fc6d6d4, Comparison=CompareOpEq, exp_data=0x1, call_count=80)
        UVM_INFO @ 20863578602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---