SRAM_CTRL/MAIN Simulation Results

Friday April 18 2025 17:34:30 UTC

GitHub Revision: 97d23b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.659m	7.916ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.120s	15.623us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.220s	103.769us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.650s	467.700us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.260s	50.200us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.950s	1.282ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.220s	103.769us	20	20	100.00
		sram_ctrl_csr_aliasing	2.260s	50.200us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.387m	82.770ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.086m	20.912ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	18.407m	76.358ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	7.632m	22.373ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	41.758m	958.043ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	21.982m	22.528ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.354m	62.453ms	50	50	100.00
V2	executable	sram_ctrl_executable	26.758m	100.154ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.696m	546.670us	50	50	100.00
		sram_ctrl_partial_access_b2b	11.379m	110.091ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.553m	800.283us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.884m	3.265ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.872m	1.909ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	19.610m	14.481ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	7.010s	2.251ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.462h	1.277s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.180s	151.948us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.060s	488.879us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.060s	488.879us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.120s	15.623us	5	5	100.00
		sram_ctrl_csr_rw	2.220s	103.769us	20	20	100.00
		sram_ctrl_csr_aliasing	2.260s	50.200us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.360s	37.913us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.120s	15.623us	5	5	100.00
		sram_ctrl_csr_rw	2.220s	103.769us	20	20	100.00
		sram_ctrl_csr_aliasing	2.260s	50.200us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.360s	37.913us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.254m	7.105ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.050s	3.641us	0	5	0.00
		sram_ctrl_tl_intg_err	5.950s	2.122ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.050s	3.641us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	5.950s	2.122ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	19.610m	14.481ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	19.610m	14.481ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.220s	103.769us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	26.758m	100.154ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	26.758m	100.154ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	26.758m	100.154ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.354m	62.453ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	10.460s	2.760ms	41	50	82.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.254m	7.105ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	13.250s	10.954ms	39	50	78.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.659m	7.916ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.659m	7.916ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	26.758m	100.154ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.050s	3.641us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.354m	62.453ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.050s	3.641us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.050s	3.641us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.659m	7.916ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.050s	3.641us	0	5	0.00
V2S		TOTAL			120	145	82.76
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.290m	2.579ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1165	1190	97.90

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	99.29	93.01	85.18	100.00	98.07	98.59	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 11 failures:
  • Test sram_ctrl_readback_err has 11 failures.

    • 4.sram_ctrl_readback_err.2012707801581403045317070671517652351871457480114999791013266272666643795498
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 687519799 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x3e) != exp (0x17)
        UVM_INFO @ 687519799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 8.sram_ctrl_readback_err.93964031260947926435038400502531663219932145537598726748727274892789916744407
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/8.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 5969014298 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x59) != exp (0x40)
        UVM_INFO @ 5969014298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 9 more failures.

• Offending 'reqfifo_rvalid' has 9 failures:
  • Test sram_ctrl_mubi_enc_err has 9 failures.

    • 2.sram_ctrl_mubi_enc_err.18165843271164703737820279897206208754199727071109752544565697386378947626410
      Line 104, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2764625869 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2764625869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.sram_ctrl_mubi_enc_err.50372665145558178026590493780918507631827440409137378399873290094423290016789
      Line 104, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2709838948 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2709838948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 7 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:
  • Test sram_ctrl_sec_cm has 4 failures.

    • 1.sram_ctrl_sec_cm.86921533896819388591516551597780467149481832252448853697925308104073444883848
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  12154623 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  12154623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.5034034680189505730133844456109794953296768556922408379426232558130320384863
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7448334 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7448334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.112366046206667430852537215867213769367586280288895736370662815799988718181005
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   3641181 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   3641181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---