SRAM_CTRL/RET Simulation Results

Friday April 18 2025 17:34:30 UTC

GitHub Revision: 97d23b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.305m	3.171ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.960s	11.537us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.100s	33.869us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.650s	163.988us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.090s	132.772us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.080s	403.931us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.100s	33.869us	20	20	100.00
		sram_ctrl_csr_aliasing	2.090s	132.772us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	15.300s	2.744ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	8.790s	3.040ms	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	22.917m	12.499ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.107m	6.479ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.400m	19.886ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	21.810m	53.463ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	14.320s	1.839ms	50	50	100.00
V2	executable	sram_ctrl_executable	25.396m	17.130ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.753m	650.570us	50	50	100.00
		sram_ctrl_partial_access_b2b	8.873m	46.894ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.450m	135.556us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.639m	313.183us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.697m	296.026us	50	50	100.00
V2	regwen	sram_ctrl_regwen	20.027m	60.568ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.310s	32.061us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.149h	123.594ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.200s	13.475us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.150s	1.281ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.150s	1.281ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.960s	11.537us	5	5	100.00
		sram_ctrl_csr_rw	2.100s	33.869us	20	20	100.00
		sram_ctrl_csr_aliasing	2.090s	132.772us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.310s	78.207us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.960s	11.537us	5	5	100.00
		sram_ctrl_csr_rw	2.100s	33.869us	20	20	100.00
		sram_ctrl_csr_aliasing	2.090s	132.772us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.310s	78.207us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.410s	6.540ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.230s	11.515us	0	5	0.00
		sram_ctrl_tl_intg_err	4.720s	3.412ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.230s	11.515us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.720s	3.412ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	20.027m	60.568ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	20.027m	60.568ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.100s	33.869us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	25.396m	17.130ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	25.396m	17.130ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	25.396m	17.130ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	14.320s	1.839ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.670s	38.559us	43	50	86.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.410s	6.540ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.630s	201.891us	35	50	70.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.305m	3.171ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.305m	3.171ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	25.396m	17.130ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.230s	11.515us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	14.320s	1.839ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.230s	11.515us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.230s	11.515us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.305m	3.171ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.230s	11.515us	0	5	0.00
V2S		TOTAL			118	145	81.38
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	8.918m	1.514ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1160	1190	97.48

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	99.26	93.01	85.10	100.00	98.03	98.58	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 15 failures:

  • Test sram_ctrl_readback_err has 15 failures.

    • 0.sram_ctrl_readback_err.106482918427508477831182527391789364805496952269360971636382979309082474509377
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  90392802 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x34) != exp (0x55)
        UVM_INFO @  90392802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.sram_ctrl_readback_err.47781943007954187112476574947460674910213070206949935338654200430571194919560
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  86633262 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x1b) != exp (0x75)
        UVM_INFO @  86633262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 13 more failures.

• Offending 'reqfifo_rvalid' has 7 failures:

  • Test sram_ctrl_mubi_enc_err has 7 failures.

    • 10.sram_ctrl_mubi_enc_err.78328099837177188488423065966538889422411486112690966148339930775832871442414
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 122210916 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 122210916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 14.sram_ctrl_mubi_enc_err.15110093094358946574298295176604161612820327456754205946976346177318365864305
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/14.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  96462895 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  96462895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 5 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 5 failures:

  • Test sram_ctrl_sec_cm has 5 failures.

    • 0.sram_ctrl_sec_cm.109036925208496584815585084141899320607663044151835122300660149879695822649224
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   8333692 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   8333692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.64161212246531152342386930001119369973819913477220433396749205633166342036432
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3613280 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3613280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 4.sram_ctrl_csr_mem_rw_with_rand_reset.68153276837452222163749551497229916249991078112414455975993256332468960251819
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 403930534 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
        UVM_INFO @ 403930534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 18.sram_ctrl_csr_mem_rw_with_rand_reset.17569727960998842207293365664324618638428818385931401306570265961795711131785
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/18.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  44885391 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @  44885391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:924) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test sram_ctrl_stress_all_with_rand_reset has 1 failures.

    • 47.sram_ctrl_stress_all_with_rand_reset.85199328863777241548959828097997667054585117993794288628745312513176102287734
      Line 110, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/47.sram_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5556500176 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5556500176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---