UART Simulation Results

Friday April 18 2025 17:34:30 UTC

GitHub Revision: 97d23b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	15.670s	5.903ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.660s	14.892us	5	5	100.00
V1	csr_rw	uart_csr_rw	1.930s	16.224us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.920s	513.622us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	1.650s	38.840us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.330s	124.226us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.930s	16.224us	20	20	100.00
		uart_csr_aliasing	1.650s	38.840us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	2.626m	96.065ms	50	50	100.00
V2	parity	uart_smoke	15.670s	5.903ms	50	50	100.00
		uart_tx_rx	2.626m	96.065ms	50	50	100.00
V2	parity_error	uart_intr	4.332m	196.514ms	50	50	100.00
		uart_rx_parity_err	5.057m	205.641ms	50	50	100.00
V2	watermark	uart_tx_rx	2.626m	96.065ms	50	50	100.00
		uart_intr	4.332m	196.514ms	50	50	100.00
V2	fifo_full	uart_fifo_full	3.892m	205.095ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	3.467m	199.092ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	7.118m	138.462ms	298	300	99.33
V2	rx_frame_err	uart_intr	4.332m	196.514ms	50	50	100.00
V2	rx_break_err	uart_intr	4.332m	196.514ms	50	50	100.00
V2	rx_timeout	uart_intr	4.332m	196.514ms	50	50	100.00
V2	perf	uart_perf	13.416m	22.718ms	49	50	98.00
V2	sys_loopback	uart_loopback	13.510s	9.038ms	50	50	100.00
V2	line_loopback	uart_loopback	13.510s	9.038ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	5.223m	149.361ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.554m	87.870ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	18.800s	7.039ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	48.030s	7.363ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	13.781m	159.030ms	50	50	100.00
V2	stress_all	uart_stress_all	13.139m	135.878ms	50	50	100.00
V2	alert_test	uart_alert_test	2.450s	118.523us	50	50	100.00
V2	intr_test	uart_intr_test	2.010s	33.807us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.010s	114.754us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.010s	114.754us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.660s	14.892us	5	5	100.00
		uart_csr_rw	1.930s	16.224us	20	20	100.00
		uart_csr_aliasing	1.650s	38.840us	5	5	100.00
		uart_same_csr_outstanding	1.970s	70.654us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.660s	14.892us	5	5	100.00
		uart_csr_rw	1.930s	16.224us	20	20	100.00
		uart_csr_aliasing	1.650s	38.840us	5	5	100.00
		uart_same_csr_outstanding	1.970s	70.654us	20	20	100.00
V2		TOTAL			1087	1090	99.72
V2S	tl_intg_err	uart_sec_cm	2.670s	68.515us	5	5	100.00
		uart_tl_intg_err	2.410s	151.995us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.410s	151.995us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.192m	11.726ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1316	1320	99.70

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.77	99.17	98.25	91.55	--	98.15	100.00	99.48

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 4 failures:

  • Test uart_perf has 1 failures.

    • 7.uart_perf.17800882380561730930466351787558217155169782992649465210031687667202179324410
      Line 78, in log /nightly/runs/scratch/master/uart-sim-vcs/7.uart_perf/latest/run.log

        UVM_ERROR @ 12419790230 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 14825224606 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 5/6
        UVM_INFO @ 15857290230 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 6/6
        UVM_INFO @ 16043290230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 36.uart_stress_all_with_rand_reset.42268714560653218835391435030012695127509353795990302991286645092338750724289
      Line 206, in log /nightly/runs/scratch/master/uart-sim-vcs/36.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11675413281 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 11697435489 ps: (cip_base_vseq.sv:832) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 10/10
        UVM_INFO @ 11697611961 ps: (cip_base_vseq.sv:852) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 10/10
      

  • Test uart_fifo_reset has 2 failures.

    • 62.uart_fifo_reset.71055561823301173500047197970072827844457380982136114918727931975917184217322
      Line 74, in log /nightly/runs/scratch/master/uart-sim-vcs/62.uart_fifo_reset/latest/run.log

        UVM_ERROR @   1239092 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 529587894 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/6
        UVM_INFO @ 1271919631 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/6
        UVM_INFO @ 2337937410 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/6
        UVM_INFO @ 3197725130 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/6
      

    • 65.uart_fifo_reset.49926959306735641243702416907025753370911135094855934170009541092742267994719
      Line 74, in log /nightly/runs/scratch/master/uart-sim-vcs/65.uart_fifo_reset/latest/run.log

        UVM_ERROR @   3554000 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 498157186 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/10
        UVM_INFO @ 1328043491 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/10
        UVM_INFO @ 2088965888 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/10
        UVM_INFO @ 2328249688 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/10