CHIP Simulation Results

Friday April 18 2025 17:34:30 UTC

GitHub Revision: `97d23b4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.485m		0	5	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.485m		0	5	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.873m		0	20	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.529m		0	5	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.411m		0	5	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.214m	6.629ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.214m	6.629ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.214m	6.629ms	3	3	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	3.224m		0	3	0.00
		chip_sw_example_manufacturer	42.005s		0	3	0.00
		chip_sw_example_concurrency	6.126m	4.264ms	3	3	100.00
		chip_sw_uart_smoketest_signed	22.083s		0	3	0.00
V1	csr_bit_bash	chip_csr_bit_bash	18.780s		0	3	0.00
V1	csr_aliasing	chip_csr_aliasing	18.270s		0	3	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	18.270s		0	3	0.00
V1	xbar_smoke	xbar_smoke	36.440s	72.155us	100	100	100.00
V1		TOTAL			106	156	67.95
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	2.212m		0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	11.478m	7.998ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	7.090m	4.253ms	0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	17.687s		0	3	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	23.093s		0	3	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	51.491s		0	3	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	35.464s		0	3	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.870s		0	10	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.870s		0	10	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.601m		0	3	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.410m		0	3	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.970m		0	6	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.970m		0	6	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	4.502m	4.548ms	0	3	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	4.804m	5.190ms	0	3	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	9.139m	15.395ms	0	3	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	21.726s		0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	19.009s		0	3	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	19.347m	22.473ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	8.538m	6.408ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	36.972m	18.018ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	36.972m	18.018ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	21.936s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	23.365s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	23.365s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	18.813s		0	5	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.889m	3.528ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	7.561m	5.206ms	3	3	100.00
		chip_sw_aes_idle	5.956m	4.844ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.912m	4.452ms	3	3	100.00
		chip_sw_kmac_idle	5.936m	4.035ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	17.428s		0	3	0.00
		chip_sw_clkmgr_off_hmac_trans	20.072s		0	3	0.00
		chip_sw_clkmgr_off_kmac_trans	20.795s		0	3	0.00
		chip_sw_clkmgr_off_otbn_trans	18.253s		0	3	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	17.731s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	17.609s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	16.405s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	19.481s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	18.343s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	17.823s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	18.251s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	17.731s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	17.609s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	16.405s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	19.481s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	18.343s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	17.823s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	18.251s		0	3	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	17.481s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.281m	10.260us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.007m	10.340us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	58.750s	10.360us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.139m	10.300us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	15.375s		0	3	0.00
		chip_sw_clkmgr_jitter	6.264m	5.374ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	6.505m	5.631ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	19.040s		0	3	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	1.034m	10.240us	0	3	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	1.365m	10.180us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	1.332m	10.120us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	1.348m	10.140us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	1.364m	10.380us	0	3	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	18.651s		0	3	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	19.022s		0	3	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	19.022s		0	3	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	17.745s		0	3	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	34.694m	15.157ms	94	100	94.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	15.196m	14.399ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	23.365s		0	3	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	19.664s		0	3	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	15.196m	14.399ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	19.205s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	16.240s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	35.489s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	24.099s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	17.133s		0	3	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	34.694m	15.157ms	94	100	94.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	9.139m	15.395ms	0	3	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	37.028m	20.024ms	0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	10.495m	9.289ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	14.168m	30.015ms	0	3	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.324m	3.527ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	34.694m	15.157ms	94	100	94.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	19.268s		0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	19.314s		0	3	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	34.694m	15.157ms	94	100	94.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	17.933s		0	3	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	14.168m	30.015ms	0	3	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	18.617s		0	3	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	22.717s		0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	18.584s		0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	17.620s		0	3	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	18.880s		0	3	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	19.057s		0	3	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	19.314s		0	3	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	18.272s		0	15	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	18.775s		0	3	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	18.272s		0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	18.272s		0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	18.272s		0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	10.058m	8.330ms	0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	23.235s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	24.296s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	20.897s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	20.835s		0	3	0.00
		chip_sw_lc_ctrl_transition	18.272s		0	15	0.00
		chip_sw_keymgr_dpe_key_derivation	11.640m	10.177ms	0	3	0.00
		chip_sw_rom_ctrl_integrity_check	13.310m	11.958ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	16.412s		0	3	0.00
		chip_prim_tl_access	18.185m	23.567ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	17.731s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	17.609s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	16.405s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	19.481s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	18.343s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	17.823s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	18.251s		0	3	0.00
		chip_rv_dm_lc_disabled	19.347m	22.473ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	6.750m	5.424ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	1.281m	10.260us	0	3	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	6.014m	4.797ms	3	3	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.956m	4.844ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	6.153m	5.342ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	1.007m	10.340us	0	3	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.912m	4.452ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.958m	4.181ms	3	3	100.00
		chip_sw_kmac_mode_kmac	7.497m	5.296ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	1.139m	10.300us	0	3	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	11.640m	10.177ms	0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	18.272s		0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	53.730s	10.380us	0	3	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	7.454m	3.625ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.936m	4.035ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	19.475s		0	3	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	19.475s		0	3	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	19.759s		0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.574m	3.657ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	17.974s		0	3	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	11.640m	10.177ms	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	58.750s	10.360us	0	3	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	20.865s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	17.481s		0	3	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	7.561m	5.206ms	3	3	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	7.561m	5.206ms	3	3	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	7.561m	5.206ms	3	3	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	9.765m	4.975ms	3	3	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	13.310m	11.958ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	13.310m	11.958ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	11.527m	7.551ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	15.375s		0	3	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	16.412s		0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	34.694m	15.157ms	94	100	94.00
		chip_sw_data_integrity_escalation	2.970m		0	6	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	18.272s		0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	9.765m	4.975ms	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	11.640m	10.177ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	11.527m	7.551ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.684m	4.711ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	9.765m	4.975ms	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	11.640m	10.177ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	11.527m	7.551ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.684m	4.711ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	18.272s		0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	19.124s		0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	18.775s		0	3	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	23.235s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	24.296s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	20.897s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	20.835s		0	3	0.00
		chip_sw_lc_ctrl_transition	18.272s		0	15	0.00
		chip_prim_tl_access	18.185m	23.567ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	18.185m	23.567ms	3	3	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	20.365s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	25.401s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	19.022s		0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	17.481s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.281m	10.260us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.007m	10.340us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	58.750s	10.360us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.139m	10.300us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	15.375s		0	3	0.00
		chip_sw_clkmgr_jitter	6.264m	5.374ms	3	3	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	11.326m	9.639ms	3	3	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	11.326m	9.639ms	3	3	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	7.818m	5.055ms	0	3	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	6.723m	4.904ms	3	3	100.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	5.877m	4.627ms	3	3	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	10.371m	5.407ms	0	3	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.417m	4.630ms	2	3	66.67
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	5.832m	4.453ms	3	3	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	5.684m	4.711ms	3	3	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	37.028m	20.024ms	0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	37.028m	20.024ms	0	3	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	6.716m	5.337ms	3	3	100.00
		chip_sw_aon_timer_smoketest	7.853m	5.594ms	3	3	100.00
		chip_sw_clkmgr_smoketest	6.115m	4.938ms	3	3	100.00
		chip_sw_csrng_smoketest	5.846m	4.527ms	3	3	100.00
		chip_sw_gpio_smoketest	6.208m	5.527ms	3	3	100.00
		chip_sw_hmac_smoketest	7.779m	5.622ms	3	3	100.00
		chip_sw_kmac_smoketest	7.501m	5.956ms	3	3	100.00
		chip_sw_otbn_smoketest	9.463m	5.304ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	6.266m	4.664ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.759m	5.477ms	3	3	100.00
		chip_sw_rv_timer_smoketest	7.936m	5.974ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.798m	5.482ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	6.069m	3.691ms	3	3	100.00
		chip_sw_uart_smoketest	5.885m	3.469ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	20.226s		0	3	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	22.083s		0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.212m		0	3	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	16.945s		0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	7.635m	5.961ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	5.316m	5.776ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.999m	6.121ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	5.669m	4.497ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	25.361s		0	3	0.00
		chip_rv_dm_lc_disabled	19.347m	22.473ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	16.560s		0	3	0.00
		chip_sw_lc_walkthrough_prod	21.622s		0	3	0.00
		chip_sw_lc_walkthrough_prodend	16.644s		0	3	0.00
		chip_sw_lc_walkthrough_rma	27.210s		0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	25.361s		0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	18.884s		0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	34.423s		0	3	0.00
		rom_volatile_raw_unlock	16.007s		0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	19.741s		0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.855m		0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.864m		0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	5.851m	4.675ms	0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors	5.851m	4.675ms	0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	18.270s		0	3	0.00
		chip_same_csr_outstanding	11.440s		0	3	0.00
V2	tl_d_partial_access	chip_csr_aliasing	18.270s		0	3	0.00
		chip_same_csr_outstanding	11.440s		0	3	0.00
V2	xbar_base_random_sequence	xbar_random	4.285m	455.236us	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	16.010s	13.465us	100	100	100.00
		xbar_smoke_large_delays	9.224m	2.572ms	100	100	100.00
		xbar_smoke_slow_rsp	10.750m	2.206ms	100	100	100.00
		xbar_random_zero_delays	2.282m	80.355us	100	100	100.00
		xbar_random_large_delays	32.811m	10.677ms	100	100	100.00
		xbar_random_slow_rsp	56.368m	14.900ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	2.831m	264.863us	100	100	100.00
		xbar_error_and_unmapped_addr	2.469m	250.869us	100	100	100.00
V2	xbar_error_cases	xbar_error_random	4.837m	543.359us	100	100	100.00
		xbar_error_and_unmapped_addr	2.469m	250.869us	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	8.852m	968.678us	100	100	100.00
		xbar_access_same_device_slow_rsp	58.821m	16.576ms	76	100	76.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	4.137m	451.294us	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	34.152m	4.679ms	100	100	100.00
		xbar_stress_all_with_error	30.635m	4.224ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	52.446m	1.627ms	98	100	98.00
		xbar_stress_all_with_reset_error	47.698m	5.463ms	99	100	99.00
V2	rom_e2e_smoke	rom_e2e_smoke	20.094s		0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	18.289s		0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	18.462s		0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	16.078s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	13.467s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	13.832s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	17.510s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	16.547s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	14.031s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	16.368s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	13.001s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	16.554s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	13.587s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.042s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	20.337s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	17.762s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	17.408s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.902s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	16.750s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	13.131s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	18.060s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	15.134s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	16.238s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	17.327s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	15.712s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	15.076s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	15.179s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	15.187s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	15.214s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.896s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	15.926s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	14.601s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	17.747s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	15.177s		0	3	0.00
		rom_e2e_asm_init_dev	18.169s		0	3	0.00
		rom_e2e_asm_init_prod	18.176s		0	3	0.00
		rom_e2e_asm_init_prod_end	17.814s		0	3	0.00
		rom_e2e_asm_init_rma	18.892s		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	17.015s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	17.959s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	17.162s		0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	16.951s		0	3	0.00
V2		TOTAL			1904	2429	78.39
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.439m	3.507ms	3	3	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	5.221m	4.758ms	3	3	100.00
V2S		TOTAL			6	6	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	16.902s		0	1	0.00
		rom_e2e_jtag_debug_dev	15.025s		0	1	0.00
		rom_e2e_jtag_debug_rma	15.261s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	17.985s		0	3	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	34.694m	15.157ms	94	100	94.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.103m		0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	24.269m	13.072ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	11.538s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	17.451s		0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	16.902s		0	1	0.00
		rom_e2e_jtag_debug_dev	15.025s		0	1	0.00
		rom_e2e_jtag_debug_rma	15.261s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	12.882s		0	1	0.00
		rom_e2e_jtag_inject_dev	14.742s		0	1	0.00
		rom_e2e_jtag_inject_rma	12.149s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.171m		0	3	0.00
V3		TOTAL			1	20	5.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	33.382m	16.793ms	3	3	100.00
		chip_plic_all_irqs_0	11.803m	5.102ms	3	3	100.00
		chip_plic_all_irqs_10	15.661m	7.568ms	3	3	100.00
		chip_sw_dma_inline_hashing	7.640m	5.504ms	3	3	100.00
		chip_sw_dma_abort	6.205m	4.828ms	0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	14.028s		0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	18.570s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	17.205s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	16.791s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	17.555s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	17.311s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	16.554s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	15.642s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	13.528s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	15.368s		0	3	0.00
		chip_sw_mbx_smoketest	8.039m	6.295ms	3	3	100.00
		TOTAL			2032	2659	76.42

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
75.56	74.55	78.12	66.21	--	80.92	66.93	86.65

Failure Buckets

Job returned non-zero exit code has 478 failures:

Test chip_sw_example_rom has 3 failures.

0.chip_sw_example_rom.7216825636276556475247168309378552959537361520670368370953852976362592074058
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  DEBUG: /nightly/runs/opentitan/rules/autogen.bzl:452:14: NOTE: stamping is disabled, the chip_info section will use a fixed version string
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (9e75a2)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (d59184)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 166.900s, Critical Path: 0.03s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_example_rom.34315530797198376727281430085634364311473056041150033079547887838065316856018
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log

  Target //sw/device/tests:example_test_from_rom_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (6f7bb3)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (9f3103)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 5.634s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_example_manufacturer has 3 failures.

0.chip_sw_example_manufacturer.51794458556183437511787606656137800117160738357096591512445814797943640975479
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (f8a0b7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 16.669s, Critical Path: 0.07s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_example_manufacturer.13361665096861274958094247548855575897189464664010190576246500773896870145634
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (385016)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 3.314s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_data_integrity_escalation has 6 failures.

0.chip_sw_data_integrity_escalation.25163991011787575155892264363680643123966531268201651581686795036770155876992
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (27c758)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 159.713s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_data_integrity_escalation.96524686169095947628802117516071956276135788428404733663446042440721934969238
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0da586)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 0.823s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 4 more failures.

Test chip_sw_sleep_pin_wake has 3 failures.

0.chip_sw_sleep_pin_wake.6052751085983403457227496829928587000903045082219549596755428962211220417475
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (ace682)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 138.810s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_sleep_pin_wake.113616650736978526103340394600204822246737985256102903941930187373105961572833
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (92ebc9)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 21.391s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_sleep_pin_retention has 3 failures.

0.chip_sw_sleep_pin_retention.97011661869515404928737505063923812810935298421722880337938155382122653488027
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (1 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (a7bfc1)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 129.630s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_sleep_pin_retention.84747554255652601481406201119559020404855431783798497350894477907430114155320
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b6178d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 3.333s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

... and 138 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 27 failures:
- Test chip_sw_aes_enc_jitter_en has 3 failures.
  - 0.chip_sw_aes_enc_jitter_en.16309227976281610621670346032829193566726072176554976445116751452268878875382
    Line 414, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aes_enc_jitter_en.48395177765762480315176055177966131877578949000598703012025095521727095003473
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_hmac_enc_jitter_en has 3 failures.
  - 0.chip_sw_hmac_enc_jitter_en.104626070367809434838075177323956983828230788778907082051236873828762155141567
    Line 418, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_hmac_enc_jitter_en.98514031906003512122319995921358241291004715424639343858037125929744932701283
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 3 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.108288072500598724918950973710605373676678621094270894067285497353292684934182
    Line 406, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_keymgr_dpe_key_derivation_jitter_en.68130956981480134506162159911186785149423766643412031283216424832567645786494
    Line 437, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_kmac_mode_kmac_jitter_en has 3 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.12188862546257400090523303506324070225742787821121031375851229822888615585122
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_kmac_mode_kmac_jitter_en.56044080293513131965333075594346865677166796851971594030177688344587553309014
    Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 3 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.79898613338518141437835331583946796330895548007605047484742829615680286583380
    Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aes_enc_jitter_en_reduced_freq.65741934790131922109855366739098482548463725520836598781992343879702791435827
    Line 420, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- ... and 4 more tests.
Job timed out after * minutes has 27 failures:
- Test xbar_access_same_device_slow_rsp has 24 failures.
  - 6.xbar_access_same_device_slow_rsp.64382167035871199767449181279849867968001769777997126171426828570255378228676
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/6.xbar_access_same_device_slow_rsp/latest/run.log
```
  Job timed out after 60 minutes
```
  - 8.xbar_access_same_device_slow_rsp.87945578828784446389780422585064899869790117480657223506125885014196170228280
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/8.xbar_access_same_device_slow_rsp/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 22 more failures.
- Test xbar_stress_all_with_reset_error has 1 failures.
  - 16.xbar_stress_all_with_reset_error.26458006081384558332332270983400937383415001838191774089114466931843619298813
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/16.xbar_stress_all_with_reset_error/latest/run.log
```
  Job timed out after 60 minutes
```
- Test xbar_stress_all_with_rand_reset has 2 failures.
  - 66.xbar_stress_all_with_rand_reset.46701996155663674888133919043801039146284233170370672261018800745323968281295
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/66.xbar_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 60 minutes
```
  - 72.xbar_stress_all_with_rand_reset.57993649211551636851569009742541820081375491066849611393786682844523545170762
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/72.xbar_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 60 minutes
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 13 failures:
- Test chip_tl_errors has 13 failures.
  - 0.chip_tl_errors.55608854285076571878204315072359774987715760499816728917313747000072641313750
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3578.479432 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3578.479432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.chip_tl_errors.112691201030195915578714781565752303077554015154253590608927593277622665682853
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/3.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4836.220408 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4836.220408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 11 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 10 failures:
- Test chip_padctrl_attributes has 10 failures.
  - 0.chip_padctrl_attributes.42891396302271970264871370124541965317297677131696164373100126509861881062612
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 1.chip_padctrl_attributes.90310862615978516872197234177390996401118218421223219769615143604737656310817
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 8 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 9 failures:
- Test chip_csr_bit_bash has 3 failures.
  - 0.chip_csr_bit_bash.35976856248926205157569881228969944924555569218766585846110686694952537161239
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_bit_bash.64171397969588007237700076832765919254974506050379396752667477089710133513969
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_csr_aliasing has 3 failures.
  - 0.chip_csr_aliasing.99873345306130445008594438572469046279049828643832179868657742255797987495919
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_aliasing.35458302351356363440386899754427843708943813551844762633353557241630274620831
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_same_csr_outstanding has 3 failures.
  - 0.chip_same_csr_outstanding.60553620038319731400156715819950968034922971640366022437942175501170386997570
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_same_csr_outstanding.32033873706955650801051238554861786545523009015360810174452399546993767784770
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 9 failures:

Test chip_sw_rstmgr_alert_info has 3 failures.

0.chip_sw_rstmgr_alert_info.23620854486572316438659404180221993216844519787937670985337872448423388096223
Line 458, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30017.985366 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30017.985366 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_rstmgr_alert_info.10454531395948000311547387301340938718226961269729493100269551715150006838049
Line 433, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30020.552562 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30020.552562 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_rstmgr_cpu_info has 3 failures.

0.chip_sw_rstmgr_cpu_info.34817954145198202550618893807290206177052096748436256466719376487277193545149
Line 494, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20016.605312 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20016.605312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_rstmgr_cpu_info.114773776926165023009061883636808913046185372688622874463554266765210218329886
Line 460, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20023.703542 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20023.703542 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_aon_timer_irq has 3 failures.

0.chip_sw_aon_timer_irq.75414671911113767480245889428341849067815581055659552653172822706149380859773
Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18015.256738 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18015.256738 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_aon_timer_irq.19065846248145932992064790762691656018765512416262039378824618754788325845981
Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18017.763956 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18017.763956 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 6 failures:

Test chip_sw_keymgr_dpe_key_derivation has 3 failures.

0.chip_sw_keymgr_dpe_key_derivation.87932322416540706525010455155909943104697556471099826974194399610295602700488
Line 473, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8109.211568 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (104988786084659147656699395698503075310429471357826417010856516016214096583208 [0xe81d8c0efbf6ef5e58692dcbd16bd6c092e9540658f457ab6d1547eebd319a28] vs 87189817528256502884092627124400841768891848567782502871996059908008973243865 [0xc0c3b01a87feaa7e508b929d072b745a400991f7fe72116a6b021cde237d15d9])
  UVM_INFO @ 8109.211568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_keymgr_dpe_key_derivation.100044793687898066959387950810168406735546385420712128831467192718338487727628
Line 496, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 10176.829392 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (42956172362440267697083892426437440536752299976819857787666699388127832093504 [0x5ef854fb5e1617d9132e18e8e426edf30ab02a05c6171c4d7c7d47950896b340] vs 27031494535006342318391309963828434203178351638705130376390792713777520890886 [0x3bc348a1ea49dab060ce7f5474d3698d5b4952a71bc8108abde50ad33508d406])
  UVM_INFO @ 10176.829392 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_keymgr_dpe_key_derivation_prod has 3 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.14316351326937369538549493038546832971836542654311864027747560512907012236388
Line 464, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 8329.656930 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (10381850061596631341270638702074161670985599482366785993942402697660645664305 [0x16f3eb3d0a361b31817d9f6e1e47181a8a2b977bcb87bae48ab7bfbae4426631] vs 81960894107760017459248345074781957271977741158215928729923540757080598804534 [0xb53438dd6747c5b78b57b6c452bd585ec2b1b9736310d8ea7e1bb68a960a7836])
  UVM_INFO @ 8329.656930 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_keymgr_dpe_key_derivation_prod.35201968000273221470356169547369110123559315573396472998872919532903878113744
Line 482, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 7058.119916 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (105734446950834045795360744814828691687031225073385154424686165688289841421245 [0xe9c39381b2171bb3e6ea152e95bf76aac83b3d5685b63f8ee7e8585474689bbd] vs 112451940242933387973641875682104626539661030233230077393651190845876136492092 [0xf89d8aec0ee8160b699dfe8bee654ad6a0e78df32fcb11369e2fd04fb9e2bc3c])
  UVM_INFO @ 7058.119916 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 6 failures:

Test chip_jtag_csr_rw has 3 failures.

0.chip_jtag_csr_rw.106171586308821789112087636581636917861730451547637030852891070800446371842303
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4199.775043 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h86c30fd4  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8  a_opcode: 'h1  a_user: 'h248b9  d_param: 'h0  d_source: 'h8  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4199.775043 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_jtag_csr_rw.8232970997599867341037634068690045961507757550979143815935076321276674152291
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4547.518836 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h1998de4a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h23  a_opcode: 'h0  a_user: 'h26974  d_param: 'h0  d_source: 'h23  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4547.518836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_jtag_mem_access has 3 failures.

0.chip_jtag_mem_access.111827579746186692488497140591191256165381624221091526332489619472587779083633
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4345.751399 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h7a33a79b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2b  a_opcode: 'h1  a_user: 'h248dc  d_param: 'h0  d_source: 'h2b  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4345.751399 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_jtag_mem_access.18439023045465217350240449253918362968777241064143538546692030203123775503285
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 5189.680475 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h7d107ddf  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h30  a_opcode: 'h0  a_user: 'h26919  d_param: 'h0  d_source: 'h30  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5189.680475 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected *, got * has 4 failures:
- Test chip_sw_all_escalation_resets has 4 failures.
  - 23.chip_sw_all_escalation_resets.80249427535172839215617310333616883845252398058020931000278845866347148627490
    Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/23.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 4388.564910 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
  UVM_INFO @ 4388.564910 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 34.chip_sw_all_escalation_resets.28596191926818384977395769101008991899841161884715085059778895862076310323594
    Line 434, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/34.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 5511.821688 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
  UVM_INFO @ 5511.821688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 3 failures:
- Test chip_sw_spi_device_pass_through_collision has 3 failures.
  - 0.chip_sw_spi_device_pass_through_collision.3235918121244740958088015982635095266330170500464207189731926951221834843995
    Line 473, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4253.326668 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4253.326668 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_spi_device_pass_through_collision.54330509967077988731031992824125908464024783258958006095232563089517497297002
    Line 439, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5761.032760 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5761.032760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 3 failures:

Test chip_sw_soc_proxy_external_alerts has 3 failures.

0.chip_sw_soc_proxy_external_alerts.57282510064908505597488064453504425842683861637983535533899665893641562309252
Line 449, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log

  UVM_ERROR @ 5054.686592 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5054.686592 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_soc_proxy_external_alerts.77884624675105402851549206040943536685272365248121438213388721123300059531498
Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_alerts/latest/run.log

  UVM_ERROR @ 4511.631210 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4511.631210 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 3 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 3 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.114947507805525922874083919572894057714711863189609843987029042622537461606465
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 4719.764960 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 4719.764960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_rv_core_ibex_nmi_irq.17784197015130268640407089445234321438559323631120518720878882410807088603546
    Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5406.962030 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5406.962030 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 3 failures:
- Test chip_sw_kmac_app_rom has 3 failures.
  - 0.chip_sw_kmac_app_rom.13302584764034805249680865855993351625892153048476224193511199562388527879639
    Line 423, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_kmac_app_rom.71350520455266499454466818425224872657738059027213669397218642487509328841143
    Line 445, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 3 failures:
- Test chip_rv_dm_ndm_reset_req has 3 failures.
  - 0.chip_rv_dm_ndm_reset_req.39217708782749348409955446874653202055769984717641196888338025794123222962328
    Line 404, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 15509.785312 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 15509.785312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_rv_dm_ndm_reset_req.34333224104750249062070890549652102434487569475565750962762768866262142913973
    Line 404, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 15395.151804 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 15395.151804 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 3 failures:

Test chip_sw_dma_abort has 3 failures.

0.chip_sw_dma_abort.50594903678509143117452967221209903977813083165084140239374171073754079200557
Line 429, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 4828.199556 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4828.199556 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_dma_abort.28118739159523386010447249023071924279275591104274442146424335215225555412825
Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 4533.664998 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4533.664998 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == * has 1 failures:
- Test chip_sw_rv_core_ibex_rnd has 1 failures.
  - 1.chip_sw_rv_core_ibex_rnd.16374658879534420176166583239062125645593165073793083665836538648188007225970
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_rnd/latest/run.log
```
  UVM_ERROR @ 4630.188024 us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == 0
  UVM_INFO @ 4630.188024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@35700) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures: