AES/MASKED Simulation Results

Friday April 25 2025 17:33:44 UTC

GitHub Revision: `f7f0ea6`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	144.296us	1	1	100.00
V1	smoke	aes_smoke	11.000s	449.783us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	6.000s	94.514us	5	5	100.00
V1	csr_rw	aes_csr_rw	6.000s	122.086us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	185.169us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	171.039us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	68.520us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	6.000s	122.086us	20	20	100.00
		aes_csr_aliasing	6.000s	171.039us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	11.000s	449.783us	50	50	100.00
		aes_config_error	17.000s	2.689ms	50	50	100.00
		aes_stress	11.000s	340.437us	50	50	100.00
V2	key_length	aes_smoke	11.000s	449.783us	50	50	100.00
		aes_config_error	17.000s	2.689ms	50	50	100.00
		aes_stress	11.000s	340.437us	50	50	100.00
V2	back2back	aes_stress	11.000s	340.437us	50	50	100.00
		aes_b2b	29.000s	469.268us	50	50	100.00
V2	backpressure	aes_stress	11.000s	340.437us	50	50	100.00
V2	multi_message	aes_smoke	11.000s	449.783us	50	50	100.00
		aes_config_error	17.000s	2.689ms	50	50	100.00
		aes_stress	11.000s	340.437us	50	50	100.00
		aes_alert_reset	22.000s	1.523ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	355.945us	50	50	100.00
		aes_config_error	17.000s	2.689ms	50	50	100.00
		aes_alert_reset	22.000s	1.523ms	50	50	100.00
V2	trigger_clear_test	aes_clear	29.000s	1.301ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	393.085us	1	1	100.00
V2	reset_recovery	aes_alert_reset	22.000s	1.523ms	50	50	100.00
V2	stress	aes_stress	11.000s	340.437us	50	50	100.00
V2	sideload	aes_stress	11.000s	340.437us	50	50	100.00
		aes_sideload	21.000s	2.183ms	50	50	100.00
V2	deinitialization	aes_deinit	12.000s	359.038us	50	50	100.00
V2	stress_all	aes_stress_all	2.083m	7.020ms	10	10	100.00
V2	alert_test	aes_alert_test	10.000s	66.113us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	1.734ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	1.734ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	6.000s	94.514us	5	5	100.00
		aes_csr_rw	6.000s	122.086us	20	20	100.00
		aes_csr_aliasing	6.000s	171.039us	5	5	100.00
		aes_same_csr_outstanding	6.000s	145.716us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	6.000s	94.514us	5	5	100.00
		aes_csr_rw	6.000s	122.086us	20	20	100.00
		aes_csr_aliasing	6.000s	171.039us	5	5	100.00
		aes_same_csr_outstanding	6.000s	145.716us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	13.000s	740.744us	50	50	100.00
V2S	fault_inject	aes_fi	20.000s	1.223ms	50	50	100.00
		aes_control_fi	45.000s	10.003ms	278	300	92.67
		aes_cipher_fi	41.000s	10.047ms	344	350	98.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	314.164us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	314.164us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	314.164us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	314.164us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	105.051us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	1.916ms	5	5	100.00
		aes_tl_intg_err	8.000s	746.128us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	746.128us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	22.000s	1.523ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	314.164us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	11.000s	449.783us	50	50	100.00
		aes_stress	11.000s	340.437us	50	50	100.00
		aes_alert_reset	22.000s	1.523ms	50	50	100.00
		aes_core_fi	37.000s	10.016ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	314.164us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	61.345us	50	50	100.00
		aes_stress	11.000s	340.437us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	11.000s	340.437us	50	50	100.00
		aes_sideload	21.000s	2.183ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	61.345us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	61.345us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	61.345us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	61.345us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	61.345us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	11.000s	340.437us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	11.000s	340.437us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	20.000s	1.223ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	20.000s	1.223ms	50	50	100.00
		aes_control_fi	45.000s	10.003ms	278	300	92.67
		aes_cipher_fi	41.000s	10.047ms	344	350	98.29
		aes_ctr_fi	7.000s	88.134us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	20.000s	1.223ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	20.000s	1.223ms	50	50	100.00
		aes_control_fi	45.000s	10.003ms	278	300	92.67
		aes_cipher_fi	41.000s	10.047ms	344	350	98.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	41.000s	10.047ms	344	350	98.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	20.000s	1.223ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	20.000s	1.223ms	50	50	100.00
		aes_control_fi	45.000s	10.003ms	278	300	92.67
		aes_ctr_fi	7.000s	88.134us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	20.000s	1.223ms	50	50	100.00
		aes_control_fi	45.000s	10.003ms	278	300	92.67
		aes_cipher_fi	41.000s	10.047ms	344	350	98.29
		aes_ctr_fi	7.000s	88.134us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	22.000s	1.523ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	20.000s	1.223ms	50	50	100.00
		aes_control_fi	45.000s	10.003ms	278	300	92.67
		aes_cipher_fi	41.000s	10.047ms	344	350	98.29
		aes_ctr_fi	7.000s	88.134us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	20.000s	1.223ms	50	50	100.00
		aes_control_fi	45.000s	10.003ms	278	300	92.67
		aes_cipher_fi	41.000s	10.047ms	344	350	98.29
		aes_ctr_fi	7.000s	88.134us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	20.000s	1.223ms	50	50	100.00
		aes_control_fi	45.000s	10.003ms	278	300	92.67
		aes_ctr_fi	7.000s	88.134us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	20.000s	1.223ms	50	50	100.00
		aes_control_fi	45.000s	10.003ms	278	300	92.67
		aes_cipher_fi	41.000s	10.047ms	344	350	98.29
V2S		TOTAL			955	985	96.95
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	29.000s	2.453ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1562	1602	97.50

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.44	98.63	96.52	99.45	95.75	98.07	97.78	98.96	99.40

Failure Buckets

Job timed out after * minutes has 14 failures:
- Test aes_control_fi has 14 failures.
  - 0.aes_control_fi.67196528390676564424002065955031729336222098454581594794653786145778077330536
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 16.aes_control_fi.29425282260597756827347114885145765229087432440368797858311809703804561782981
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 12 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 1.aes_control_fi.62366576644475055114846070712106533795575520814369533118768363746961058742635
    Line 140, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005407201 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005407201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 75.aes_control_fi.734670891365801576909644521132325666866632041004831886137442494719006468485
    Line 140, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/75.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006236887 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006236887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.64189215650935978003148797485588564070246227485716126519448235495082139961741
Line 772, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3594133905 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3594133905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.104725912035505649104066390061784961856063745483904464942274416559192275145866
Line 446, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2453218494 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2453218494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 27.aes_cipher_fi.46277871531112795132019906427327294351923516167072286147929298488152426401237
    Line 138, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/27.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011771484 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011771484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 170.aes_cipher_fi.98441274658167430454095702556179108623584049920864377889396409653798942367835
    Line 138, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/170.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10038116442 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10038116442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 20.aes_core_fi.14434688147488303053864462252398303150677943109600624099433366619016031814531
    Line 142, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/20.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10037140195 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10037140195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 28.aes_core_fi.14089158763177765078552879921385293840468419135021199076822417235460191335394
    Line 138, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/28.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015896861 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015896861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.66180960576825808130633677863661976603462250926826391590800329028156339246547
    Line 200, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 115802935 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 115802935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.72022515121557411886313464024317411185373973104350685783034749981719688199491
    Line 280, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 193700988 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 193700988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.75351294428265442086095227585392158837830514017397365909677115503033534716777
    Line 432, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 422557505 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 422557505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```