AES/UNMASKED Simulation Results

Friday April 25 2025 17:33:44 UTC

GitHub Revision: `f7f0ea6`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	10.000s	112.674us	1	1	100.00
V1	smoke	aes_smoke	10.000s	109.286us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	115.238us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	59.781us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	533.389us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	508.419us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	101.540us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	59.781us	20	20	100.00
		aes_csr_aliasing	6.000s	508.419us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	10.000s	109.286us	50	50	100.00
		aes_config_error	8.000s	114.383us	50	50	100.00
		aes_stress	8.000s	84.299us	50	50	100.00
V2	key_length	aes_smoke	10.000s	109.286us	50	50	100.00
		aes_config_error	8.000s	114.383us	50	50	100.00
		aes_stress	8.000s	84.299us	50	50	100.00
V2	back2back	aes_stress	8.000s	84.299us	50	50	100.00
		aes_b2b	10.000s	112.301us	50	50	100.00
V2	backpressure	aes_stress	8.000s	84.299us	50	50	100.00
V2	multi_message	aes_smoke	10.000s	109.286us	50	50	100.00
		aes_config_error	8.000s	114.383us	50	50	100.00
		aes_stress	8.000s	84.299us	50	50	100.00
		aes_alert_reset	6.000s	93.914us	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	70.829us	50	50	100.00
		aes_config_error	8.000s	114.383us	50	50	100.00
		aes_alert_reset	6.000s	93.914us	50	50	100.00
V2	trigger_clear_test	aes_clear	9.000s	512.685us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	842.404us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	93.914us	50	50	100.00
V2	stress	aes_stress	8.000s	84.299us	50	50	100.00
V2	sideload	aes_stress	8.000s	84.299us	50	50	100.00
		aes_sideload	6.000s	60.504us	50	50	100.00
V2	deinitialization	aes_deinit	10.000s	116.993us	50	50	100.00
V2	stress_all	aes_stress_all	26.000s	1.349ms	10	10	100.00
V2	alert_test	aes_alert_test	5.000s	65.383us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	225.989us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	225.989us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	115.238us	5	5	100.00
		aes_csr_rw	5.000s	59.781us	20	20	100.00
		aes_csr_aliasing	6.000s	508.419us	5	5	100.00
		aes_same_csr_outstanding	6.000s	169.904us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	115.238us	5	5	100.00
		aes_csr_rw	5.000s	59.781us	20	20	100.00
		aes_csr_aliasing	6.000s	508.419us	5	5	100.00
		aes_same_csr_outstanding	6.000s	169.904us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	8.000s	238.209us	50	50	100.00
V2S	fault_inject	aes_fi	16.617m	200.000ms	48	50	96.00
		aes_control_fi	35.000s	10.004ms	273	300	91.00
		aes_cipher_fi	30.000s	10.026ms	320	350	91.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	808.158us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	808.158us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	808.158us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	808.158us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	282.045us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	1.597ms	5	5	100.00
		aes_tl_intg_err	7.000s	848.792us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	848.792us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	93.914us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	808.158us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	10.000s	109.286us	50	50	100.00
		aes_stress	8.000s	84.299us	50	50	100.00
		aes_alert_reset	6.000s	93.914us	50	50	100.00
		aes_core_fi	4.050m	10.008ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	808.158us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	55.335us	50	50	100.00
		aes_stress	8.000s	84.299us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	8.000s	84.299us	50	50	100.00
		aes_sideload	6.000s	60.504us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	55.335us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	55.335us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	55.335us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	55.335us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	55.335us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	8.000s	84.299us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	8.000s	84.299us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	16.617m	200.000ms	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	16.617m	200.000ms	48	50	96.00
		aes_control_fi	35.000s	10.004ms	273	300	91.00
		aes_cipher_fi	30.000s	10.026ms	320	350	91.43
		aes_ctr_fi	6.000s	65.258us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	16.617m	200.000ms	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	16.617m	200.000ms	48	50	96.00
		aes_control_fi	35.000s	10.004ms	273	300	91.00
		aes_cipher_fi	30.000s	10.026ms	320	350	91.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	30.000s	10.026ms	320	350	91.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	16.617m	200.000ms	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	16.617m	200.000ms	48	50	96.00
		aes_control_fi	35.000s	10.004ms	273	300	91.00
		aes_ctr_fi	6.000s	65.258us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	16.617m	200.000ms	48	50	96.00
		aes_control_fi	35.000s	10.004ms	273	300	91.00
		aes_cipher_fi	30.000s	10.026ms	320	350	91.43
		aes_ctr_fi	6.000s	65.258us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	93.914us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	16.617m	200.000ms	48	50	96.00
		aes_control_fi	35.000s	10.004ms	273	300	91.00
		aes_cipher_fi	30.000s	10.026ms	320	350	91.43
		aes_ctr_fi	6.000s	65.258us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	16.617m	200.000ms	48	50	96.00
		aes_control_fi	35.000s	10.004ms	273	300	91.00
		aes_cipher_fi	30.000s	10.026ms	320	350	91.43
		aes_ctr_fi	6.000s	65.258us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	16.617m	200.000ms	48	50	96.00
		aes_control_fi	35.000s	10.004ms	273	300	91.00
		aes_ctr_fi	6.000s	65.258us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	16.617m	200.000ms	48	50	96.00
		aes_control_fi	35.000s	10.004ms	273	300	91.00
		aes_cipher_fi	30.000s	10.026ms	320	350	91.43
V2S		TOTAL			922	985	93.60
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	23.000s	3.174ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1529	1602	95.44

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.26	97.62	94.64	98.80	93.34	97.99	91.85	98.65	98.19

Failure Buckets

Job timed out after * minutes has 27 failures:
- Test aes_cipher_fi has 14 failures.
  - 4.aes_cipher_fi.60270521724082835957586832633435854689749539691494443318241576920142079564055
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 19.aes_cipher_fi.36001313303535839378536844392831981051965261435800159122602364681561023727966
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 12 more failures.
- Test aes_control_fi has 13 failures.
  - 54.aes_control_fi.38598159272217149288804763449636478030295247228520861123882684379491481078841
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/54.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 73.aes_control_fi.112108957615091248160234417014054511293248069995621799173245321533948931629253
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/73.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 11 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 16 failures:
- Test aes_cipher_fi has 16 failures.
  - 14.aes_cipher_fi.98486173593595417254880608764899150592168444956172614804740523232597069472075
    Line 139, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010793060 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010793060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 47.aes_cipher_fi.57581290664154553254190042339635253277323642999870665937778569785950976051209
    Line 141, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/47.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011192430 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011192430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 14 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 14 failures:
- Test aes_control_fi has 14 failures.
  - 22.aes_control_fi.108192049718586446426458638613761250335549134386701532109072671955196799186908
    Line 142, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012104930 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012104930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 23.aes_control_fi.16539787493467294531855821122580344945422738173283764005139739457718483043563
    Line 140, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/23.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004687284 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004687284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 12 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.83215986650318756875285454650992573917230852365627676226480622839771503875784
Line 250, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 751058581 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 751058581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.40990697257457661668922494605377618580515860159881413877171315231795524170753
Line 705, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2033673215 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2033673215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 15.aes_core_fi.23195050918136615975926477134648468552329390854821563963373155868847071256660
    Line 131, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/15.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10041116437 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10041116437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 47.aes_core_fi.51576433907910036610672511425145904269136907154133868649311263392624853814699
    Line 129, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/47.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011318387 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011318387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:929) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.70504325691743937721880368331283942983039757495880992425903684250051468473206
    Line 397, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 964102990 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 964102990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.65550449722837843695005299787412093740927737540066578949298621483754145786833
    Line 280, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 284322268 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 284322268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.59620968006316520853422131228524997127120139419499181061757456936345713270307
    Line 138, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  52143391 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  52143391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 14.aes_fi.31105317847496117534281039422940190484298346332167890637116316123621202143330
    Line 6145, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/14.aes_fi/latest/run.log
```
  UVM_FATAL @  24361743 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  24361743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_fi has 1 failures.
  - 36.aes_fi.83958846576462180626240539581437915731017437293132153919296621442447567910853
    Line 11999209, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/36.aes_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 50.aes_core_fi.114449800275629322554270342261922342037920492716473062525950019032366085696471
    Line 133, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/50.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007889948 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xf1fb6284, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10007889948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 68.aes_core_fi.57054068030183994389988039368411333511500818492907827589958027469727913392093
    Line 143, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/68.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004579655 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004579655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```