CSRNG Simulation Results

Friday April 25 2025 17:33:44 UTC

GitHub Revision: f7f0ea6

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	244.016us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	52.000s	35.666us	5	5	100.00
V1	csr_rw	csrng_csr_rw	52.000s	53.390us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	1.133m	715.581us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	59.000s	430.502us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	52.000s	20.698us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	52.000s	53.390us	20	20	100.00
		csrng_csr_aliasing	59.000s	430.502us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	25.000s	1.289ms	199	200	99.50
V2	alerts	csrng_alert	1.083m	3.874ms	500	500	100.00
V2	err	csrng_err	7.000s	21.649us	500	500	100.00
V2	cmds	csrng_cmds	7.300m	38.025ms	50	50	100.00
V2	life cycle	csrng_cmds	7.300m	38.025ms	50	50	100.00
V2	stress_all	csrng_stress_all	19.833m	60.016ms	49	50	98.00
V2	intr_test	csrng_intr_test	52.000s	42.890us	50	50	100.00
V2	alert_test	csrng_alert_test	8.000s	117.761us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	56.000s	159.150us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	56.000s	159.150us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	52.000s	35.666us	5	5	100.00
		csrng_csr_rw	52.000s	53.390us	20	20	100.00
		csrng_csr_aliasing	59.000s	430.502us	5	5	100.00
		csrng_same_csr_outstanding	53.000s	32.936us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	52.000s	35.666us	5	5	100.00
		csrng_csr_rw	52.000s	53.390us	20	20	100.00
		csrng_csr_aliasing	59.000s	430.502us	5	5	100.00
		csrng_same_csr_outstanding	53.000s	32.936us	20	20	100.00
V2		TOTAL			1438	1440	99.86
V2S	tl_intg_err	csrng_sec_cm	8.000s	489.535us	5	5	100.00
		csrng_tl_intg_err	57.000s	296.413us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	7.000s	66.671us	50	50	100.00
		csrng_csr_rw	52.000s	53.390us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.083m	3.874ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	19.833m	60.016ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	25.000s	1.289ms	199	200	99.50
		csrng_err	7.000s	21.649us	500	500	100.00
		csrng_sec_cm	8.000s	489.535us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	25.000s	1.289ms	199	200	99.50
		csrng_err	7.000s	21.649us	500	500	100.00
		csrng_sec_cm	8.000s	489.535us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	25.000s	1.289ms	199	200	99.50
		csrng_err	7.000s	21.649us	500	500	100.00
		csrng_sec_cm	8.000s	489.535us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	25.000s	1.289ms	199	200	99.50
		csrng_err	7.000s	21.649us	500	500	100.00
		csrng_sec_cm	8.000s	489.535us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	25.000s	1.289ms	199	200	99.50
		csrng_err	7.000s	21.649us	500	500	100.00
		csrng_sec_cm	8.000s	489.535us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	25.000s	1.289ms	199	200	99.50
		csrng_err	7.000s	21.649us	500	500	100.00
		csrng_sec_cm	8.000s	489.535us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	25.000s	1.289ms	199	200	99.50
		csrng_err	7.000s	21.649us	500	500	100.00
		csrng_sec_cm	8.000s	489.535us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.083m	3.874ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	25.000s	1.289ms	199	200	99.50
		csrng_err	7.000s	21.649us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	19.833m	60.016ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.083m	3.874ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	57.000s	296.413us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	25.000s	1.289ms	199	200	99.50
		csrng_err	7.000s	21.649us	500	500	100.00
		csrng_sec_cm	8.000s	489.535us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	25.000s	1.289ms	199	200	99.50
		csrng_err	7.000s	21.649us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	25.000s	1.289ms	199	200	99.50
		csrng_err	7.000s	21.649us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	25.000s	1.289ms	199	200	99.50
		csrng_err	7.000s	21.649us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	25.000s	1.289ms	199	200	99.50
		csrng_err	7.000s	21.649us	500	500	100.00
		csrng_sec_cm	8.000s	489.535us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	25.000s	1.289ms	199	200	99.50
		csrng_err	7.000s	21.649us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.467m	8.182ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1618	1630	99.26

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.70	98.56	96.51	99.88	97.36	92.02	100.00	97.01	91.03

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:

  • Test csrng_stress_all_with_rand_reset has 10 failures.

    • 0.csrng_stress_all_with_rand_reset.20256890324703898008752191026621103293704503214021510653659242055605118229833
      Line 99, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 439576963 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 439576963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.csrng_stress_all_with_rand_reset.41114537521103334784926033903321029638088076891339382632561210746506548515708
      Line 111, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 736173632 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 736173632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:

  • Test csrng_stress_all has 1 failures.

    • 8.csrng_stress_all.54043401217126445735348654683543272625627218173792315638425602840553016686080
      Line 132, in log /nightly/runs/scratch/master/csrng-sim-xcelium/8.csrng_stress_all/latest/run.log

        UVM_ERROR @ 663214447 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 663214447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 1 failures:

  • Test csrng_intr has 1 failures.

    • 177.csrng_intr.3077460125978170153346294015702488352279570568339529117637084030175917606450
      Line 133, in log /nightly/runs/scratch/master/csrng-sim-xcelium/177.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 123664784 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
        UVM_ERROR @ 123664784 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
        UVM_INFO @ 123664784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---