DMA Simulation Results

Friday April 25 2025 17:33:44 UTC

GitHub Revision: f7f0ea6

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	12.000s	1.284ms	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	14.000s	532.072us	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	12.000s	497.411us	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	5.000s	56.657us	5	5	100.00
V1	csr_rw	dma_csr_rw	5.000s	41.872us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	18.000s	1.030ms	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	12.000s	891.767us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	5.000s	46.364us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	5.000s	41.872us	20	20	100.00
		dma_csr_aliasing	12.000s	891.767us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	2.267m	12.732ms	5	5	100.00
V2	dma_handshake_stress	dma_handshake_stress	2.467m	49.428ms	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	9.600m	45.429ms	2	3	66.67
V2	dma_generic_stress	dma_generic_stress	55.250m	3.868s	5	5	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	2.467m	49.428ms	3	3	100.00
V2	dma_abort	dma_abort	19.000s	16.850ms	5	5	100.00
V2	dma_stress_all	dma_stress_all	3.967m	290.392ms	3	3	100.00
V2	intr_test	dma_intr_test	5.000s	50.869us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	7.000s	571.629us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	7.000s	571.629us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	5.000s	56.657us	5	5	100.00
		dma_csr_rw	5.000s	41.872us	20	20	100.00
		dma_csr_aliasing	12.000s	891.767us	5	5	100.00
		dma_same_csr_outstanding	6.000s	481.826us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	5.000s	56.657us	5	5	100.00
		dma_csr_rw	5.000s	41.872us	20	20	100.00
		dma_csr_aliasing	12.000s	891.767us	5	5	100.00
		dma_same_csr_outstanding	6.000s	481.826us	20	20	100.00
V2		TOTAL			113	114	99.12
V2S	dma_illegal_addr_range	dma_mem_enabled	35.000s	921.918us	5	5	100.00
		dma_generic_stress	55.250m	3.868s	5	5	100.00
		dma_handshake_stress	2.467m	49.428ms	3	3	100.00
V2S	tl_intg_err	dma_tl_intg_err	7.000s	428.224us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	dma_short_transfer	2.983m	28.704ms	5	5	100.00
		dma_longer_transfer	14.000s	712.664us	5	5	100.00
		TOTAL			303	304	99.67

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
75.75	96.98	95.20	96.93	95.97	82.72	82.76	97.77	41.44

Failure Buckets

• Job timed out after * minutes has 1 failures:
  • Test dma_memory_stress has 1 failures.

    • 2.dma_memory_stress.300236968029884299795167398971838388580235927624357648262802011461457721729
      Log /nightly/runs/scratch/master/dma-sim-xcelium/2.dma_memory_stress/latest/run.log

        Job timed out after 60 minutes