EDN Simulation Results

Friday April 25 2025 17:33:44 UTC

GitHub Revision: f7f0ea6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 3.520s 41.724us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 2.390s 26.067us 5 5 100.00
V1 csr_rw edn_csr_rw 2.440s 27.699us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.240s 458.210us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 3.360s 376.690us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.840s 483.719us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.440s 27.699us 20 20 100.00
edn_csr_aliasing 3.360s 376.690us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 6.100s 761.351us 300 300 100.00
V2 csrng_commands edn_genbits 6.100s 761.351us 300 300 100.00
V2 genbits edn_genbits 6.100s 761.351us 300 300 100.00
V2 interrupts edn_intr 3.630s 30.270us 50 50 100.00
V2 alerts edn_alert 3.640s 24.457us 200 200 100.00
V2 errs edn_err 3.700s 35.522us 100 100 100.00
V2 disable edn_disable 3.430s 37.497us 50 50 100.00
edn_disable_auto_req_mode 3.810s 46.544us 50 50 100.00
V2 stress_all edn_stress_all 6.760s 255.767us 50 50 100.00
V2 intr_test edn_intr_test 2.590s 16.367us 50 50 100.00
V2 alert_test edn_alert_test 3.930s 33.348us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.630s 379.838us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.630s 379.838us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 2.390s 26.067us 5 5 100.00
edn_csr_rw 2.440s 27.699us 20 20 100.00
edn_csr_aliasing 3.360s 376.690us 5 5 100.00
edn_same_csr_outstanding 2.330s 19.079us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 2.390s 26.067us 5 5 100.00
edn_csr_rw 2.440s 27.699us 20 20 100.00
edn_csr_aliasing 3.360s 376.690us 5 5 100.00
edn_same_csr_outstanding 2.330s 19.079us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 8.370s 501.586us 5 5 100.00
edn_tl_intg_err 3.860s 130.766us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 3.750s 20.098us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 3.640s 24.457us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.370s 501.586us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.370s 501.586us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.370s 501.586us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.370s 501.586us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 3.640s 24.457us 200 200 100.00
edn_sec_cm 8.370s 501.586us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 3.640s 24.457us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.860s 130.766us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 2.280m 7.051ms 34 50 68.00
V3 TOTAL 34 50 68.00
TOTAL 1114 1130 98.58

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.75 98.32 94.29 97.07 91.28 96.36 99.78 93.13

Failure Buckets