HMAC Simulation Results

Friday April 25 2025 17:33:44 UTC

GitHub Revision: f7f0ea6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	16.540s	882.116us	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.340s	89.470us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.470s	34.137us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.850s	1.068ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.400s	447.297us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	3.010m	58.693ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.470s	34.137us	20	20	100.00
		hmac_csr_aliasing	9.400s	447.297us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.222m	17.741ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.359m	3.751ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.237m	12.721ms	30	30	100.00
		hmac_test_sha384_vectors	9.037m	104.475ms	75	75	100.00
		hmac_test_sha512_vectors	8.991m	63.610ms	75	75	100.00
		hmac_test_hmac256_vectors	18.060s	2.557ms	50	50	100.00
		hmac_test_hmac384_vectors	17.200s	1.498ms	60	60	100.00
		hmac_test_hmac512_vectors	19.620s	1.548ms	75	75	100.00
V2	burst_wr	hmac_burst_wr	43.990s	882.499us	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	18.319m	13.329ms	10	10	100.00
V2	error	hmac_error	1.584m	6.394ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.804m	3.312ms	10	10	100.00
V2	save_and_restore	hmac_smoke	16.540s	882.116us	10	10	100.00
		hmac_long_msg	1.222m	17.741ms	10	10	100.00
		hmac_back_pressure	1.359m	3.751ms	25	25	100.00
		hmac_datapath_stress	18.319m	13.329ms	10	10	100.00
		hmac_burst_wr	43.990s	882.499us	50	50	100.00
		hmac_stress_all	35.076m	48.989ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	16.540s	882.116us	10	10	100.00
		hmac_long_msg	1.222m	17.741ms	10	10	100.00
		hmac_back_pressure	1.359m	3.751ms	25	25	100.00
		hmac_datapath_stress	18.319m	13.329ms	10	10	100.00
		hmac_wipe_secret	1.804m	3.312ms	10	10	100.00
		hmac_test_sha256_vectors	4.237m	12.721ms	30	30	100.00
		hmac_test_sha384_vectors	9.037m	104.475ms	75	75	100.00
		hmac_test_sha512_vectors	8.991m	63.610ms	75	75	100.00
		hmac_test_hmac256_vectors	18.060s	2.557ms	50	50	100.00
		hmac_test_hmac384_vectors	17.200s	1.498ms	60	60	100.00
		hmac_test_hmac512_vectors	19.620s	1.548ms	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	16.540s	882.116us	10	10	100.00
		hmac_long_msg	1.222m	17.741ms	10	10	100.00
		hmac_back_pressure	1.359m	3.751ms	25	25	100.00
		hmac_datapath_stress	18.319m	13.329ms	10	10	100.00
		hmac_burst_wr	43.990s	882.499us	50	50	100.00
		hmac_error	1.584m	6.394ms	10	10	100.00
		hmac_wipe_secret	1.804m	3.312ms	10	10	100.00
		hmac_test_sha256_vectors	4.237m	12.721ms	30	30	100.00
		hmac_test_sha384_vectors	9.037m	104.475ms	75	75	100.00
		hmac_test_sha512_vectors	8.991m	63.610ms	75	75	100.00
		hmac_test_hmac256_vectors	18.060s	2.557ms	50	50	100.00
		hmac_test_hmac384_vectors	17.200s	1.498ms	60	60	100.00
		hmac_test_hmac512_vectors	19.620s	1.548ms	75	75	100.00
		hmac_stress_all	35.076m	48.989ms	50	50	100.00
V2	stress_all	hmac_stress_all	35.076m	48.989ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.090s	24.769us	50	50	100.00
V2	intr_test	hmac_intr_test	2.220s	111.282us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.080s	72.147us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.080s	72.147us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.340s	89.470us	5	5	100.00
		hmac_csr_rw	2.470s	34.137us	20	20	100.00
		hmac_csr_aliasing	9.400s	447.297us	5	5	100.00
		hmac_same_csr_outstanding	4.130s	145.138us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.340s	89.470us	5	5	100.00
		hmac_csr_rw	2.470s	34.137us	20	20	100.00
		hmac_csr_aliasing	9.400s	447.297us	5	5	100.00
		hmac_same_csr_outstanding	4.130s	145.138us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	2.330s	85.052us	5	5	100.00
		hmac_tl_intg_err	5.010s	237.763us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.010s	237.763us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	16.540s	882.116us	10	10	100.00
V3	stress_reset	hmac_stress_reset	8.870s	523.015us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	8.834m	24.349ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	2.020s	11.487us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.07	100.00	97.20	100.00	100.00	100.00	100.00	47.30