f7f0ea6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.557m | 2.304ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 34.770s | 8.612ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 2.110s | 25.087us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 2.160s | 64.144us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.820s | 420.204us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 3.130s | 1.426ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 2.700s | 38.864us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 2.160s | 64.144us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 3.130s | 1.426ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 9.180s | 874.440us | 48 | 50 | 96.00 |
| V2 | host_stress_all | i2c_host_stress_all | 25.975m | 126.813ms | 17 | 50 | 34.00 |
| V2 | host_maxperf | i2c_host_perf | 18.552m | 71.208ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 2.230s | 115.460us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 4.991m | 20.515ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 2.631m | 17.750ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.720s | 2.144ms | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 22.380s | 7.467ms | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 13.370s | 983.327us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.282m | 3.729ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 38.330s | 1.744ms | 50 | 50 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 7.620s | 742.765us | 16 | 50 | 32.00 |
| V2 | target_glitch | i2c_target_glitch | 16.280s | 8.647ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 42.255m | 93.032ms | 47 | 50 | 94.00 |
| V2 | target_maxperf | i2c_target_perf | 9.840s | 3.727ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.549m | 2.011ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 12.330s | 1.477ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 3.910s | 300.529us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 3.520s | 278.975us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 14.083m | 62.344ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.549m | 2.011ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 5.704m | 22.417ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 11.300s | 14.543ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 1.434m | 2.052ms | 45 | 50 | 90.00 |
| V2 | bad_address | i2c_target_bad_addr | 9.610s | 4.686ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 47.800s | 10.082ms | 23 | 50 | 46.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 5.340s | 2.541ms | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 3.120s | 290.025us | 48 | 50 | 96.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 18.552m | 71.208ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 6.008m | 23.206ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 38.330s | 1.744ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 18.460s | 1.318ms | 48 | 50 | 96.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 4.970s | 1.013ms | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 5.310s | 5.600ms | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 3.630s | 228.305us | 35 | 50 | 70.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 26.200s | 4.123ms | 50 | 50 | 100.00 |
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 4.680s | 1.117ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 2.170s | 60.647us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 2.380s | 15.899us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.420s | 469.651us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.420s | 469.651us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 2.110s | 25.087us | 5 | 5 | 100.00 |
| i2c_csr_rw | 2.160s | 64.144us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 3.130s | 1.426ms | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 2.560s | 110.651us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 2.110s | 25.087us | 5 | 5 | 100.00 |
| i2c_csr_rw | 2.160s | 64.144us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 3.130s | 1.426ms | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 2.560s | 110.651us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1669 | 1792 | 93.14 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 3.310s | 569.001us | 20 | 20 | 100.00 |
| i2c_sec_cm | 2.180s | 247.742us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 3.310s | 569.001us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 33.110s | 2.244ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 4.320s | 1.903ms | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 38.320s | 3.550ms | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1849 | 2042 | 90.55 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 88.05 | 97.41 | 89.89 | 74.17 | 72.62 | 94.41 | 98.52 | 89.32 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 41 failures:
3.i2c_host_stress_all.106160717761535295638849425931551575314278141903347365848838120398639409965736
Line 161, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 14829066264 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4229024
7.i2c_host_stress_all.98672609884387806218350100380667019378007824114969105976950344549402242057216
Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 19260669866 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @1725440
... and 23 more failures.
3.i2c_host_mode_toggle.81433202209516804332448314657956736629595586552924130191974040990611293153830
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 46093987 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @21089
8.i2c_host_mode_toggle.67127881958792132305740379637393655135909108741007634330863070883642335186844
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 725045841 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @23273
... and 14 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 34 failures:
0.i2c_target_unexp_stop.35646465339571452972561740558678721987255176773763583743474115068257187511123
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 202543863 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 88 [0x58])
UVM_INFO @ 202543863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_unexp_stop.19575412252699357001465002528602480291352645632575604381915049457260581082642
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 17716448 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 170 [0xaa])
UVM_INFO @ 17716448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 31 more failures.
0.i2c_target_stress_all_with_rand_reset.18999813204253744509555813286480725035754163058458258722228484481540505911172
Line 109, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 302779703 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 201 [0xc9])
UVM_INFO @ 302779703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 27 failures:
0.i2c_target_hrst.9169428212785398867894886787703739135594813620568816597394034811556803050206
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10105032564 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10105032564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_hrst.15047801841447547219908100259423395554674242062746668622535796026937988408263
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10234578169 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10234578169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
0.i2c_host_stress_all_with_rand_reset.10696135951828578961759676008570815752852654313850730279824390059785673790616
Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1414202135 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1414202135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.48063794640349583794720073561549381337227622930496625046945365326491971182877
Line 85, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2244450765 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2244450765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
1.i2c_target_stress_all_with_rand_reset.8477771610117816125502391463735676091692089127768783422827139038318201499091
Line 91, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 910706217 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 910706217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.60215935582464144517826780753218766184680020763306652903364086618649047830896
Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 260777099 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 260777099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 15 failures:
0.i2c_target_nack_txstretch.56337282915361804238868829762061709393335103409179258169256058106470221334579
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 180932449 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 180932449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_target_nack_txstretch.52590700544546033098651888026117272468897243063381019344506046767884692488380
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 1094144955 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 1094144955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 14 failures:
1.i2c_host_mode_toggle.16187592822228603072033367565434946264715522990837620958494745656664798318668
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 179803745 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
5.i2c_host_mode_toggle.54104040611167819517851234370060525730688900326058863860334664397243558084553
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 95056844 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 12 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 14 failures:
3.i2c_target_unexp_stop.42049639385402738788987678593500445300286764625075383000092864629674371303767
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 207347739 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 207347739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.i2c_target_unexp_stop.31945598240785638168747094260182940874941931917652266838115997805900467665021
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 245483540 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 245483540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 6 failures:
0.i2c_host_stress_all.641906642898079781864160887006913548590105020858136003221584504301573421314
Line 214, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 18415536187 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @4130710
8.i2c_host_stress_all.23387900333762414553271977461468614234759965633672633548410451834949808878466
Line 122, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 8190195419 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3439654
... and 4 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 5 failures:
13.i2c_target_stretch.88026319575823321771801159208366558386722654467720713091599503950544108825336
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/13.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10001368332 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10001368332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.i2c_target_stretch.3787619951246654587356116790016763079499903534555313541828679133615877947342
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/23.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10027071634 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10027071634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
Test i2c_target_tx_stretch_ctrl has 2 failures.
14.i2c_target_tx_stretch_ctrl.18187975131224171895921405703280557857351202166297787032109455615380758146066
Line 124, in log /nightly/runs/scratch/master/i2c-sim-vcs/14.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
37.i2c_target_tx_stretch_ctrl.10275199643818725247779714561985857973148605471294512953601827126820930374098
Line 124, in log /nightly/runs/scratch/master/i2c-sim-vcs/37.i2c_target_tx_stretch_ctrl/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
Test i2c_target_fifo_watermarks_tx has 2 failures.
20.i2c_target_fifo_watermarks_tx.97832842786432026373247896920395061773570975966344848618587256624031378665280
Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/20.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
45.i2c_target_fifo_watermarks_tx.110312969768893261809859971394710321189391643864426021885767966500741253974546
Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/45.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 3 failures:
5.i2c_target_stress_all.113953468221334219725762530923701076004469496202707970701958144165309966101605
Line 104, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 41775643345 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 41775643345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.i2c_target_stress_all.103986203314090399187055845793920480734912388203670713905996359610936361673501
Line 76, in log /nightly/runs/scratch/master/i2c-sim-vcs/17.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 37487452762 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 37487452762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 3 failures:
9.i2c_target_unexp_stop.30903910446165654570401315326420908731686343560774687470094148043738406093866
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/9.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 261194671 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 261194671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.i2c_target_unexp_stop.4732948996504226721709189400894913317955315033339185533749495116580286347763
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/21.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 2074431310 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 2074431310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
19.i2c_host_mode_toggle.20030523176297521759121804106697887643166288873146062898391623411395023483855
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/19.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 142298680 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x25925294, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 142298680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.i2c_host_mode_toggle.75196450456919326295837247604018847822853861675648588433704194959457960892566
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/42.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 111989212 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x6057ec94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 111989212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job timed out after * minutes has 2 failures:
Test i2c_host_error_intr has 1 failures.
6.i2c_host_error_intr.23743879603554948044823656736936068100511323587605519739935167885722804927184
Log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_host_error_intr/latest/run.log
Job timed out after 60 minutes
Test i2c_host_stress_all has 1 failures.
18.i2c_host_stress_all.96487537445646533034388339009780267517628873414955621988847268512666770249024
Log /nightly/runs/scratch/master/i2c-sim-vcs/18.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
UVM_ERROR (cip_base_vseq.sv:832) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
7.i2c_target_stress_all_with_rand_reset.82055043459512195153303899752621880532271836555483097024116826145748491057851
Line 84, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2377092327 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2377092327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_stress_all_with_rand_reset.88834669829231871593732199208716523790859020151901860753521918028903180867917
Line 131, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3550126551 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3550126551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
4.i2c_host_stress_all.7240696385416967318964849590984122084299506051840766221348032360157415146479
Line 89, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite has 1 failures:
5.i2c_host_error_intr.59919787850258267342330882376958404386016789158736517430323030595818926605738
Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 66703533 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpWrite
--> EXP:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
Error-[NOA] Null object access has 1 failures:
11.i2c_host_mode_toggle.7156682746416530076835329691204951074723145684678795925348770669504648117901
Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/11.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.