KEYMGR Simulation Results

Friday April 25 2025 17:33:44 UTC

GitHub Revision: `f7f0ea6`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	24.480s	1.237ms	50	50	100.00
V1	random	keymgr_random	48.430s	3.906ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.980s	36.142us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.550s	20.014us	19	20	95.00
V1	csr_bit_bash	keymgr_csr_bit_bash	11.730s	252.300us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	7.450s	442.571us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.070s	66.431us	14	20	70.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.550s	20.014us	19	20	95.00
		keymgr_csr_aliasing	7.450s	442.571us	5	5	100.00
V1		TOTAL			148	155	95.48
V2	cfgen_during_op	keymgr_cfg_regwen	1.496m	9.875ms	50	50	100.00
V2	sideload	keymgr_sideload	21.990s	873.814us	49	50	98.00
		keymgr_sideload_kmac	33.430s	3.080ms	50	50	100.00
		keymgr_sideload_aes	26.610s	3.024ms	50	50	100.00
		keymgr_sideload_otbn	45.720s	3.443ms	49	50	98.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	27.780s	4.517ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	17.550s	809.617us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	17.170s	2.913ms	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	50.820s	4.401ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	46.200s	7.144ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	13.300s	2.579ms	50	50	100.00
V2	stress_all	keymgr_stress_all	3.740m	46.577ms	49	50	98.00
V2	intr_test	keymgr_intr_test	2.370s	132.508us	50	50	100.00
V2	alert_test	keymgr_alert_test	2.540s	27.878us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.260s	486.729us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.260s	486.729us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.980s	36.142us	5	5	100.00
		keymgr_csr_rw	2.550s	20.014us	19	20	95.00
		keymgr_csr_aliasing	7.450s	442.571us	5	5	100.00
		keymgr_same_csr_outstanding	4.530s	1.228ms	14	20	70.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.980s	36.142us	5	5	100.00
		keymgr_csr_rw	2.550s	20.014us	19	20	95.00
		keymgr_csr_aliasing	7.450s	442.571us	5	5	100.00
		keymgr_same_csr_outstanding	4.530s	1.228ms	14	20	70.00
V2		TOTAL			730	740	98.65
V2S	sec_cm_additional_check	keymgr_sec_cm	14.480s	481.893us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	14.480s	481.893us	5	5	100.00
		keymgr_tl_intg_err	7.250s	783.188us	14	20	70.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.080s	368.713us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.080s	368.713us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.080s	368.713us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.080s	368.713us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	13.410s	472.715us	15	20	75.00
V2S	prim_count_check	keymgr_sec_cm	14.480s	481.893us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	14.480s	481.893us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.250s	783.188us	14	20	70.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.080s	368.713us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.496m	9.875ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	48.430s	3.906ms	50	50	100.00
		keymgr_csr_rw	2.550s	20.014us	19	20	95.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	48.430s	3.906ms	50	50	100.00
		keymgr_csr_rw	2.550s	20.014us	19	20	95.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	48.430s	3.906ms	50	50	100.00
		keymgr_csr_rw	2.550s	20.014us	19	20	95.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	17.550s	809.617us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	46.200s	7.144ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	46.200s	7.144ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	48.430s	3.906ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	21.130s	2.330ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	14.480s	481.893us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	14.480s	481.893us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	14.480s	481.893us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	55.060s	6.766ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	17.550s	809.617us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	14.480s	481.893us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	14.480s	481.893us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	14.480s	481.893us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	55.060s	6.766ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	55.060s	6.766ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	14.480s	481.893us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	55.060s	6.766ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	14.480s	481.893us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	55.060s	6.766ms	50	50	100.00
V2S		TOTAL			154	165	93.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	23.570s	2.484ms	36	50	72.00
V3		TOTAL			36	50	72.00
		TOTAL			1068	1110	96.22

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.80	99.10	97.91	98.65	100.00	99.11	98.63	91.23

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 24 failures:

Test keymgr_tl_intg_err has 6 failures.

0.keymgr_tl_intg_err.95658998052068802055826232928977954188497424080834296417640306392360219349543
Line 85, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
  UVM_ERROR @  13158315 ps: (keymgr_csr_assert_fpv.sv:416) [ASSERT FAILED] sealing_sw_binding_5_rd_A
  UVM_INFO @  13158315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.keymgr_tl_intg_err.74084418361593398432805468732347251224926734681487842652859761823026260051428
Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
  UVM_ERROR @  76816021 ps: (keymgr_csr_assert_fpv.sv:461) [ASSERT FAILED] attest_sw_binding_6_rd_A
  UVM_INFO @  76816021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test keymgr_shadow_reg_errors_with_csr_rw has 5 failures.

1.keymgr_shadow_reg_errors_with_csr_rw.93687486988041793239804086620114376230603842412930391965217059703825160183302
Line 79, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
  UVM_ERROR @ 156832523 ps: (keymgr_csr_assert_fpv.sv:461) [ASSERT FAILED] attest_sw_binding_6_rd_A
  UVM_INFO @ 156832523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.keymgr_shadow_reg_errors_with_csr_rw.96671189094731878246892546527112148680665261682581362103139100254641070153049
Line 78, in log /nightly/runs/scratch/master/keymgr-sim-vcs/6.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[13] & 'hffffffff)))'
  UVM_ERROR @   9601154 ps: (keymgr_csr_assert_fpv.sv:431) [ASSERT FAILED] attest_sw_binding_0_rd_A
  UVM_INFO @   9601154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test keymgr_csr_mem_rw_with_rand_reset has 6 failures.

1.keymgr_csr_mem_rw_with_rand_reset.44251062010871608759744143748470522651932916533435062249230975107210528516858
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
  UVM_ERROR @  26865191 ps: (keymgr_csr_assert_fpv.sv:466) [ASSERT FAILED] attest_sw_binding_7_rd_A
  UVM_INFO @  26865191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.keymgr_csr_mem_rw_with_rand_reset.8441567983630140767024221176967937029777666954012926688033995098678490297029
Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
  UVM_ERROR @  66431273 ps: (keymgr_csr_assert_fpv.sv:416) [ASSERT FAILED] sealing_sw_binding_5_rd_A
  UVM_INFO @  66431273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test keymgr_same_csr_outstanding has 6 failures.

4.keymgr_same_csr_outstanding.58842366121766309636137304057607997204217274359571842264309120733638971992484
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
  UVM_ERROR @ 118850229 ps: (keymgr_csr_assert_fpv.sv:456) [ASSERT FAILED] attest_sw_binding_5_rd_A
  UVM_INFO @ 118850229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.keymgr_same_csr_outstanding.16408665566019726132172522968335114398391779122308055670152954372496813472013
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
  UVM_ERROR @  12914863 ps: (keymgr_csr_assert_fpv.sv:441) [ASSERT FAILED] attest_sw_binding_2_rd_A
  UVM_INFO @  12914863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test keymgr_csr_rw has 1 failures.

19.keymgr_csr_rw.45398304887383503057085258839837128373963240879943951254735212814044474343582
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/19.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
  UVM_ERROR @   9427399 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_2_rd_A
  UVM_INFO @   9427399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 14 failures:
- Test keymgr_stress_all_with_rand_reset has 14 failures.
  - 0.keymgr_stress_all_with_rand_reset.70624493572596033512293858203825152206041638899839099133969823032528573626214
    Line 143, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 406373417 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 406373417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.keymgr_stress_all_with_rand_reset.26204380008955097916172277148632420975260080787227314508715733788645779261957
    Line 412, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2013633547 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2013633547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 12 more failures.

UVM_ERROR (cip_base_scoreboard.sv:349) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:

Test keymgr_sideload has 1 failures.

10.keymgr_sideload.76707178452048006032219361155826099372298614385582993720105937253451198419456
Line 216, in log /nightly/runs/scratch/master/keymgr-sim-vcs/10.keymgr_sideload/latest/run.log

  UVM_ERROR @ 333456130 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 333456130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_kmac_rsp_err has 1 failures.

29.keymgr_kmac_rsp_err.53573973706986583360360976453210386325405467717727597482945462577889319115960
Line 111, in log /nightly/runs/scratch/master/keymgr-sim-vcs/29.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  12789847 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  12789847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sideload_otbn has 1 failures.

48.keymgr_sideload_otbn.74950665996684826736291998894685670775495071575842190328569089122893398212736
Line 87, in log /nightly/runs/scratch/master/keymgr-sim-vcs/48.keymgr_sideload_otbn/latest/run.log

  UVM_ERROR @   9901057 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   9901057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerIntKey for Sealing Aes has 1 failures:

Test keymgr_stress_all has 1 failures.

31.keymgr_stress_all.3919544142322309604359369778951644769277491776175617921726252559117763368718
Line 994, in log /nightly/runs/scratch/master/keymgr-sim-vcs/31.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 1329085993 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (3822388471261471319309067829439331717869081156327527137926760996302774201787756296726382052427521151486971789238093605078302923483869364752462014293983541 [0x48fb7216a549e64422035e14280da870f5b9688b5e44db3da2f7fdeeb3af4052002d2404e8d333f8b24f53f89c897eb779758d894f56ce1d47e0c4f88f47c135] vs 3822388471261471319309067829439331717869081156327527137926760996302774201787756296726382052427521151486971789238093605078302923483869364752462014293983541 [0x48fb7216a549e64422035e14280da870f5b9688b5e44db3da2f7fdeeb3af4052002d2404e8d333f8b24f53f89c897eb779758d894f56ce1d47e0c4f88f47c135]) AES key at state StOwnerIntKey for Sealing Aes
  UVM_INFO @ 1329085993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---