KMAC/MASKED Simulation Results

Friday April 25 2025 17:33:44 UTC

GitHub Revision: `f7f0ea6`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.576m	4.889ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.630s	61.076us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.740s	30.359us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	16.990s	4.998ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.820s	560.654us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.930s	78.966us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.740s	30.359us	20	20	100.00
		kmac_csr_aliasing	8.820s	560.654us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.150s	78.297us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.980s	37.387us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	57.688m	609.091ms	50	50	100.00
V2	burst_write	kmac_burst_write	26.321m	292.574ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	37.205m	258.771ms	5	5	100.00
		kmac_test_vectors_sha3_256	36.299m	364.162ms	5	5	100.00
		kmac_test_vectors_sha3_384	30.069m	273.140ms	5	5	100.00
		kmac_test_vectors_sha3_512	21.785m	129.705ms	5	5	100.00
		kmac_test_vectors_shake_128	43.085m	72.400ms	5	5	100.00
		kmac_test_vectors_shake_256	31.853m	75.279ms	4	5	80.00
		kmac_test_vectors_kmac	3.950s	82.719us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.220s	343.401us	5	5	100.00
V2	sideload	kmac_sideload	7.951m	15.867ms	50	50	100.00
V2	app	kmac_app	6.373m	28.057ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.543m	29.730ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.703m	29.792ms	50	50	100.00
V2	error	kmac_error	7.865m	21.244ms	49	50	98.00
V2	key_error	kmac_key_error	18.140s	6.288ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	11.360s	1.096ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	46.610s	1.438ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	43.980s	7.656ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.159m	7.038ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	54.060s	883.959us	50	50	100.00
V2	stress_all	kmac_stress_all	36.641m	28.923ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.380s	13.201us	50	50	100.00
V2	alert_test	kmac_alert_test	2.350s	42.775us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.320s	141.852us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.320s	141.852us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.630s	61.076us	5	5	100.00
		kmac_csr_rw	2.740s	30.359us	20	20	100.00
		kmac_csr_aliasing	8.820s	560.654us	5	5	100.00
		kmac_same_csr_outstanding	4.350s	826.804us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.630s	61.076us	5	5	100.00
		kmac_csr_rw	2.740s	30.359us	20	20	100.00
		kmac_csr_aliasing	8.820s	560.654us	5	5	100.00
		kmac_same_csr_outstanding	4.350s	826.804us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.140s	546.323us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.140s	546.323us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.140s	546.323us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.140s	546.323us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.810s	152.794us	13	20	65.00
V2S	tl_intg_err	kmac_sec_cm	1.798m	8.207ms	5	5	100.00
		kmac_tl_intg_err	6.100s	1.347ms	15	20	75.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.100s	1.347ms	15	20	75.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	54.060s	883.959us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.576m	4.889ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.951m	15.867ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.140s	546.323us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.798m	8.207ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.798m	8.207ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.798m	8.207ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.576m	4.889ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	54.060s	883.959us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.798m	8.207ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.090m	13.683ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.576m	4.889ms	50	50	100.00
V2S		TOTAL			63	75	84.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.054m	3.646ms	6	10	60.00
V3		TOTAL			6	10	60.00
		TOTAL			922	940	98.09

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.49	99.09	94.47	99.89	80.99	97.05	99.06	97.86

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 12 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 7 failures.

0.kmac_shadow_reg_errors_with_csr_rw.33768581034101695106426788522212651831837626203265542733213733435524630444313
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
  UVM_ERROR @  36914420 ps: (kmac_csr_assert_fpv.sv:487) [ASSERT FAILED] entropy_period_rd_A
  UVM_INFO @  36914420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.kmac_shadow_reg_errors_with_csr_rw.83481053971729418044593528951090437329327184209043856087479952715095384167927
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
  UVM_ERROR @  23486464 ps: (kmac_csr_assert_fpv.sv:502) [ASSERT FAILED] prefix_2_rd_A
  UVM_INFO @  23486464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test kmac_tl_intg_err has 5 failures.

1.kmac_tl_intg_err.59788066001024280803430961971418881455184128400377682347743819929758440296516
Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
  UVM_ERROR @   9904686 ps: (kmac_csr_assert_fpv.sv:537) [ASSERT FAILED] prefix_9_rd_A
  UVM_INFO @   9904686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.kmac_tl_intg_err.8419628543220359751861720408679892754782425266043939977962476364637281736031
Line 82, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/4.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
  UVM_ERROR @  15406316 ps: (kmac_csr_assert_fpv.sv:487) [ASSERT FAILED] entropy_period_rd_A
  UVM_INFO @  15406316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 1.kmac_stress_all_with_rand_reset.26912041633668502924868693906130282699646131630148351401618800673759232888407
    Line 90, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 393729263 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 393729263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.kmac_stress_all_with_rand_reset.82065062948685665181986403236015311114906818914549223809312027148790600460864
    Line 114, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3767829249 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 3767829249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
- Test kmac_test_vectors_shake_256 has 1 failures.
  - 0.kmac_test_vectors_shake_256.26324288543438088311064317459928466061113587900274700471555054959089972225279
    Line 73, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest/run.log
```
  UVM_ERROR @ 133160267 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 133160267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 37.kmac_error.4230759746777641000437781602522046385327838032986076486510792074641287514860
    Line 224, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/37.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```