KMAC/UNMASKED Simulation Results

Friday April 25 2025 17:33:44 UTC

GitHub Revision: `f7f0ea6`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.152m	57.899ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.600s	316.710us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.650s	104.477us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.000s	1.717ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.410s	1.354ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	4.080s	295.364us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.650s	104.477us	20	20	100.00
		kmac_csr_aliasing	8.410s	1.354ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.170s	42.722us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.930s	36.266us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	35.218m	107.498ms	50	50	100.00
V2	burst_write	kmac_burst_write	15.482m	72.802ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	18.861m	17.820ms	5	5	100.00
		kmac_test_vectors_sha3_256	25.838m	57.385ms	5	5	100.00
		kmac_test_vectors_sha3_384	19.600m	67.572ms	5	5	100.00
		kmac_test_vectors_sha3_512	10.326m	11.022ms	5	5	100.00
		kmac_test_vectors_shake_128	37.453m	546.461ms	5	5	100.00
		kmac_test_vectors_shake_256	27.962m	233.028ms	5	5	100.00
		kmac_test_vectors_kmac	3.900s	262.550us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.770s	83.429us	5	5	100.00
V2	sideload	kmac_sideload	6.820m	76.869ms	50	50	100.00
V2	app	kmac_app	5.320m	38.960ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.543m	12.161ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.983m	15.469ms	50	50	100.00
V2	error	kmac_error	6.635m	29.820ms	50	50	100.00
V2	key_error	kmac_key_error	14.160s	10.809ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.183m	10.036ms	35	50	70.00
V2	edn_timeout_error	kmac_edn_timeout_error	35.380s	9.138ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	41.620s	1.587ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	44.520s	14.141ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	39.140s	1.805ms	50	50	100.00
V2	stress_all	kmac_stress_all	43.646m	1.072s	50	50	100.00
V2	intr_test	kmac_intr_test	2.280s	57.248us	50	50	100.00
V2	alert_test	kmac_alert_test	2.270s	20.967us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.270s	175.483us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.270s	175.483us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.600s	316.710us	5	5	100.00
		kmac_csr_rw	2.650s	104.477us	20	20	100.00
		kmac_csr_aliasing	8.410s	1.354ms	5	5	100.00
		kmac_same_csr_outstanding	4.560s	1.346ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.600s	316.710us	5	5	100.00
		kmac_csr_rw	2.650s	104.477us	20	20	100.00
		kmac_csr_aliasing	8.410s	1.354ms	5	5	100.00
		kmac_same_csr_outstanding	4.560s	1.346ms	20	20	100.00
V2		TOTAL			725	740	97.97
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.320s	89.651us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.320s	89.651us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.320s	89.651us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.320s	89.651us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.450s	200.645us	12	20	60.00
V2S	tl_intg_err	kmac_sec_cm	55.280s	11.168ms	5	5	100.00
		kmac_tl_intg_err	6.040s	731.915us	16	20	80.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.040s	731.915us	16	20	80.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	39.140s	1.805ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.152m	57.899ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.820m	76.869ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.320s	89.651us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	55.280s	11.168ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	55.280s	11.168ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	55.280s	11.168ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.152m	57.899ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	39.140s	1.805ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	55.280s	11.168ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.314m	9.147ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.152m	57.899ms	50	50	100.00
V2S		TOTAL			63	75	84.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	6.852m	28.597ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			910	940	96.81

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.67	97.18	94.42	100.00	72.73	95.93	99.02	96.41

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 12 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 8 failures.

0.kmac_shadow_reg_errors_with_csr_rw.46149137952077255861587874357348843411486149272563912778551554347941650413060
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[49] & 'hffffffff)))'
  UVM_ERROR @  28948374 ps: (kmac_csr_assert_fpv.sv:542) [ASSERT FAILED] prefix_10_rd_A
  UVM_INFO @  28948374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_shadow_reg_errors_with_csr_rw.20887538423284208458642774003776140127896285542789886418951738756891573895163
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
  UVM_ERROR @  55258911 ps: (kmac_csr_assert_fpv.sv:497) [ASSERT FAILED] prefix_1_rd_A
  UVM_INFO @  55258911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test kmac_tl_intg_err has 4 failures.

3.kmac_tl_intg_err.1619579838847041823585818972274384595071348620961463235866873428619412745661
Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
  UVM_ERROR @  28368698 ps: (kmac_csr_assert_fpv.sv:497) [ASSERT FAILED] prefix_1_rd_A
  UVM_INFO @  28368698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.kmac_tl_intg_err.81132047109198115916034227847216477147255166470703127260432817251354061220515
Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/9.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
  UVM_ERROR @   9828462 ps: (kmac_csr_assert_fpv.sv:492) [ASSERT FAILED] prefix_0_rd_A
  UVM_INFO @   9828462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 4 failures:
- Test kmac_sideload_invalid has 4 failures.
  - 5.kmac_sideload_invalid.69918312072764980654924300067611305723802959183602083251969588911806622555220
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10084161922 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2b924000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10084161922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 21.kmac_sideload_invalid.41322049181515662468916027238665873127994222550761446150838034134084736861913
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/21.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10012925507 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x77bbe000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10012925507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 3 failures:
- Test kmac_sideload_invalid has 3 failures.
  - 14.kmac_sideload_invalid.23920478239459433936121265458037487589895581854361852396434708167794163180259
    Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/14.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10036499708 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2727f000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
  UVM_INFO @ 10036499708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 25.kmac_sideload_invalid.105593969812938137711778146345118247495356450672846750236187036565521553117417
    Line 81, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/25.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10109914043 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xc3557000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
  UVM_INFO @ 10109914043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 1.kmac_sideload_invalid.34952914676452779798765287918665918464727065152696057694660319970241714015572
    Line 87, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10419163224 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3f4a5000, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
  UVM_INFO @ 10419163224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.kmac_sideload_invalid.24146157830623676954985651807194947064962113141195815631304774215639248259948
    Line 87, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10466554718 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6f678000, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
  UVM_INFO @ 10466554718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 2.kmac_stress_all_with_rand_reset.114446093821209995378570398887277701992351280458477032249129013208108478773325
    Line 102, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 193106671 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 193106671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.kmac_stress_all_with_rand_reset.91095522991775530315384872194284188114860528708343105011810839817424528571459
    Line 120, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3574149130 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483656 [0x80000008]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 3574149130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 4.kmac_sideload_invalid.6617685074948256195877409401003860580002752337163439535391337660547135826301
    Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10914278438 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x83587000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
  UVM_INFO @ 10914278438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 4.kmac_stress_all_with_rand_reset.28991949151394630223196780753777838895825142821136646449787820627840568416414
    Line 77, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5314859977 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5314859977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 10.kmac_sideload_invalid.53007969271292594177464008121124947254261367802473335124187541038141709561008
    Line 91, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/10.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10127654376 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x40c27000, Comparison=CompareOpEq, exp_data=0x1, call_count=19)
  UVM_INFO @ 10127654376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 18.kmac_sideload_invalid.13923977490096155235914092208064574054687760294798420150010531871722565147528
    Line 74, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/18.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10086254169 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7e5a0000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 10086254169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 19.kmac_sideload_invalid.7002727880330477228724023867530570517207481004860247643385410768821818110767
    Line 81, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/19.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10605185920 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x278cb000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
  UVM_INFO @ 10605185920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 24.kmac_sideload_invalid.53814431727751233471856483421251972486523375240028461431783581607616463233732
    Line 90, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/24.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10521570847 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x3aac0000, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
  UVM_INFO @ 10521570847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 45.kmac_sideload_invalid.46648347974683834714809312330763229079327220430934157221364517638110511823494
    Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/45.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10104207552 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x67dba000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
  UVM_INFO @ 10104207552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```