MBX Simulation Results

Friday April 25 2025 17:33:44 UTC

GitHub Revision: f7f0ea6

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 mbx_smoke mbx_smoke 1.350m 3.589ms 2 2 100.00
V1 csr_hw_reset mbx_csr_hw_reset 5.000s 45.527us 5 5 100.00
V1 csr_rw mbx_csr_rw 5.000s 33.685us 20 20 100.00
V1 csr_bit_bash mbx_csr_bit_bash 6.000s 188.623us 5 5 100.00
V1 csr_aliasing mbx_csr_aliasing 5.000s 32.649us 5 5 100.00
V1 csr_mem_rw_with_rand_reset mbx_csr_mem_rw_with_rand_reset 5.000s 17.441us 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr mbx_csr_rw 5.000s 33.685us 20 20 100.00
mbx_csr_aliasing 5.000s 32.649us 5 5 100.00
V1 TOTAL 37 57 64.91
V2 mbx_stress mbx_stress 1.183m 1.290ms 2 2 100.00
mbx_stress_zero_delays 57.000s 368.163us 2 2 100.00
V2 mbx_imbx_oob mbx_imbx_oob 47.000s 528.537us 1 2 50.00
V2 alert_test mbx_alert_test 42.000s 128.409us 50 50 100.00
V2 tl_d_oob_addr_access mbx_tl_errors 5.000s 9.378us 0 20 0.00
V2 tl_d_illegal_access mbx_tl_errors 5.000s 9.378us 0 20 0.00
V2 tl_d_outstanding_access mbx_csr_hw_reset 5.000s 45.527us 5 5 100.00
mbx_csr_rw 5.000s 33.685us 20 20 100.00
mbx_csr_aliasing 5.000s 32.649us 5 5 100.00
mbx_same_csr_outstanding 5.000s 29.208us 20 20 100.00
V2 tl_d_partial_access mbx_csr_hw_reset 5.000s 45.527us 5 5 100.00
mbx_csr_rw 5.000s 33.685us 20 20 100.00
mbx_csr_aliasing 5.000s 32.649us 5 5 100.00
mbx_same_csr_outstanding 5.000s 29.208us 20 20 100.00
V2 TOTAL 75 96 78.12
V2S tl_intg_err mbx_sec_cm 42.000s 19.920us 5 5 100.00
mbx_tl_intg_err 5.000s 9.324us 0 20 0.00
V2S TOTAL 5 25 20.00
TOTAL 117 178 65.73

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
90.43 96.78 92.27 96.66 79.76 85.25 -- 97.08 63.09

Failure Buckets