OTBN Simulation Results

Friday April 25 2025 17:33:44 UTC

GitHub Revision: `f7f0ea6`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	63.683us	1	1	100.00
V1	single_binary	otbn_single	1.283m	244.501us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	13.000s	12.355us	5	5	100.00
V1	csr_rw	otbn_csr_rw	9.000s	18.802us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	319.630us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	9.000s	23.828us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	14.000s	37.450us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	9.000s	18.802us	20	20	100.00
		otbn_csr_aliasing	9.000s	23.828us	5	5	100.00
V1	mem_walk	otbn_mem_walk	38.000s	779.099us	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	28.000s	396.070us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	53.000s	137.940us	9	10	90.00
V2	multi_error	otbn_multi_err	1.700m	904.808us	1	1	100.00
V2	back_to_back	otbn_multi	3.283m	787.816us	10	10	100.00
V2	stress_all	otbn_stress_all	4.450m	2.434ms	10	10	100.00
V2	lc_escalation	otbn_escalate	2.383m	627.696us	59	60	98.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	13.000s	36.078us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	1.083m	228.066us	10	10	100.00
V2	alert_test	otbn_alert_test	9.000s	20.285us	50	50	100.00
V2	intr_test	otbn_intr_test	25.000s	26.862us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	51.000s	61.731us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	51.000s	61.731us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	13.000s	12.355us	5	5	100.00
		otbn_csr_rw	9.000s	18.802us	20	20	100.00
		otbn_csr_aliasing	9.000s	23.828us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	36.390us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	13.000s	12.355us	5	5	100.00
		otbn_csr_rw	9.000s	18.802us	20	20	100.00
		otbn_csr_aliasing	9.000s	23.828us	5	5	100.00
		otbn_same_csr_outstanding	11.000s	36.390us	20	20	100.00
V2		TOTAL			244	246	99.19
V2S	mem_integrity	otbn_imem_err	13.000s	36.175us	10	10	100.00
		otbn_dmem_err	15.000s	27.014us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	12.000s	200.701us	5	5	100.00
		otbn_controller_ispr_rdata_err	16.000s	80.135us	5	5	100.00
		otbn_mac_bignum_acc_err	14.000s	32.416us	5	5	100.00
		otbn_urnd_err	9.000s	46.849us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	16.000s	61.555us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	11.000s	19.489us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	13.000s	38.442us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	4.483m	2.059ms	3	5	60.00
		otbn_tl_intg_err	49.000s	191.995us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.067m	95.339us	18	20	90.00
V2S	prim_fsm_check	otbn_sec_cm	4.483m	2.059ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	4.483m	2.059ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	63.683us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	15.000s	27.014us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	13.000s	36.175us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	49.000s	191.995us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	2.383m	627.696us	59	60	98.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	13.000s	36.175us	10	10	100.00
		otbn_dmem_err	15.000s	27.014us	15	15	100.00
		otbn_zero_state_err_urnd	13.000s	36.078us	5	5	100.00
		otbn_illegal_mem_acc	16.000s	61.555us	5	5	100.00
		otbn_sec_cm	4.483m	2.059ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	4.483m	2.059ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.283m	244.501us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	13.000s	36.175us	10	10	100.00
		otbn_dmem_err	15.000s	27.014us	15	15	100.00
		otbn_zero_state_err_urnd	13.000s	36.078us	5	5	100.00
		otbn_illegal_mem_acc	16.000s	61.555us	5	5	100.00
		otbn_sec_cm	4.483m	2.059ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	4.483m	2.059ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	2.383m	627.696us	59	60	98.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	13.000s	36.175us	10	10	100.00
		otbn_dmem_err	15.000s	27.014us	15	15	100.00
		otbn_zero_state_err_urnd	13.000s	36.078us	5	5	100.00
		otbn_illegal_mem_acc	16.000s	61.555us	5	5	100.00
		otbn_sec_cm	4.483m	2.059ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	4.483m	2.059ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.283m	244.501us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	36.000s	126.307us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	13.000s	30.102us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.667m	916.272us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.667m	916.272us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	62.443us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	4.483m	2.059ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	4.483m	2.059ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	14.000s	61.956us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	4.483m	2.059ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	4.483m	2.059ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	20.000s	112.798us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	20.000s	112.798us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	19.000s	42.253us	4	7	57.14
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.283m	244.501us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.283m	244.501us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.283m	244.501us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	3.283m	787.816us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.283m	244.501us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.283m	244.501us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	21.000s	107.608us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.283m	244.501us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	4.483m	2.059ms	3	5	60.00
V2S		TOTAL			156	163	95.71
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	7.350m	1.571ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			571	585	97.61

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.06	99.59	95.31	99.70	93.07	93.73	97.44	97.04	100.00

Failure Buckets

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_sec_wipe_err has 3 failures.

0.otbn_sec_wipe_err.42180371863010219275065014458167108980517303950304026655729386813150564076264
Line 116, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 71536531 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  71536531 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  71536531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.otbn_sec_wipe_err.65089437904078966918719070446144858905080128443100649040536555730448450553962
Line 109, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 78018600 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  78018600 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  78018600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test otbn_escalate has 1 failures.

47.otbn_escalate.74246059765497139269518270937279719922488473285259077591488779126036028356907
Line 112, in log /nightly/runs/scratch/master/otbn-sim-xcelium/47.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 14628962 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  14628962 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  14628962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 3.otbn_stress_all_with_rand_reset.47886204716836864815330236122295411321832264057974713599413354495104266900003
    Line 227, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1285199883 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1285199883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.otbn_stress_all_with_rand_reset.110100316819580154101935105117338816597937964818646471914693231035824384529736
    Line 276, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1440272139 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1440272139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 3 failures:

Test otbn_stress_all_with_rand_reset has 1 failures.

9.otbn_stress_all_with_rand_reset.102164680459062803879810727985863921353102714844228895102385806359658473758198
Line 156, in log /nightly/runs/scratch/master/otbn-sim-xcelium/9.otbn_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 334460678 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @ 334460678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_passthru_mem_tl_intg_err has 2 failures.

11.otbn_passthru_mem_tl_intg_err.97003576773276264171887576742493353479623498676122958029517622338877518353112
Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/11.otbn_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @   7360638 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @   7360638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.otbn_passthru_mem_tl_intg_err.88572720325378679570640065680910068782424317319050539834172428508117790330513
Line 87, in log /nightly/runs/scratch/master/otbn-sim-xcelium/17.otbn_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @  77032898 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @  77032898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

2.otbn_sec_cm.97616975667140111301301981283158098415919843945229566520269300505884827133071
Line 91, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 35014201 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 35014201 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @  35014201 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @  35014201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.otbn_sec_cm.60255143038934081379673428945846379798223006110962330428971320514808997279637
Line 94, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 30790070 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 30790070 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @  30790070 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @  30790070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 1.otbn_stress_all_with_rand_reset.96235658677044802857011828306856627728512826540803971317066661883232973869430
    Line 404, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2087005971 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 2087005971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:384) [otbn_reset_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution has 1 failures:
- Test otbn_reset has 1 failures.
  - 4.otbn_reset.1348832815012564042962033574941776505510658589696372177462854351224862282088
    Line 106, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_reset/latest/run.log
```
  UVM_FATAL @  51693457 ps: (otbn_base_vseq.sv:384) [uvm_test_top.env.virtual_sequencer.otbn_reset_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusIdle) Timed out waiting for OTBN to be idle before execution
  UVM_INFO @  51693457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```