ROM_CTRL/32KB Simulation Results

Friday April 25 2025 17:33:44 UTC

GitHub Revision: f7f0ea6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	8.950s	568.817us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.870s	131.076us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	9.040s	2.014ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.530s	171.191us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.630s	2.296ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	9.790s	2.024ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	9.040s	2.014ms	20	20	100.00
		rom_ctrl_csr_aliasing	6.630s	2.296ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.530s	558.410us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.840s	995.322us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.430s	140.535us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	27.760s	5.054ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	14.760s	309.059us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	9.110s	3.119ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	13.240s	1.701ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	13.240s	1.701ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.870s	131.076us	5	5	100.00
		rom_ctrl_csr_rw	9.040s	2.014ms	20	20	100.00
		rom_ctrl_csr_aliasing	6.630s	2.296ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	10.280s	182.212us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.870s	131.076us	5	5	100.00
		rom_ctrl_csr_rw	9.040s	2.014ms	20	20	100.00
		rom_ctrl_csr_aliasing	6.630s	2.296ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	10.280s	182.212us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.198m	1.158ms	2	20	10.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	35.440s	1.627ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.517m	1.604ms	5	5	100.00
		rom_ctrl_tl_intg_err	1.099m	586.366us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.517m	1.604ms	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.517m	1.604ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.198m	1.158ms	2	20	10.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.198m	1.158ms	2	20	10.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.198m	1.158ms	2	20	10.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.198m	1.158ms	2	20	10.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.198m	1.158ms	2	20	10.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.517m	1.604ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.517m	1.604ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	8.950s	568.817us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	8.950s	568.817us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	8.950s	568.817us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.099m	586.366us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.198m	1.158ms	2	20	10.00
		rom_ctrl_kmac_err_chk	14.760s	309.059us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.198m	1.158ms	2	20	10.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.198m	1.158ms	2	20	10.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.198m	1.158ms	2	20	10.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	35.440s	1.627ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.517m	1.604ms	5	5	100.00
V2S		TOTAL			47	65	72.31
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	8.788m	4.840ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			248	266	93.23

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.61	100.00	99.27	100.00	93.33	99.65	98.97	99.05

Failure Buckets

• Job timed out after * minutes has 16 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 16 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.29657131155616564862138931956229178303524572908778650971483307091673028115557
      Log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        Job timed out after 60 minutes
      

    • 4.rom_ctrl_corrupt_sig_fatal_chk.26303589484109797997420419615262005007724715795566871687775559862980151644388
      Log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        Job timed out after 60 minutes
      

    • ... and 14 more failures.

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 2 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 2 failures.

    • 2.rom_ctrl_corrupt_sig_fatal_chk.99606054429648944480664903718782445193782311848787771475454146017555547822184
      Line 77, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 524364275 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 524364275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.rom_ctrl_corrupt_sig_fatal_chk.6824507711648599665640792656217303052359413989589726332577291520211807709429
      Line 81, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/6.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 1423947488 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 1423947488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---