RV_TIMER Simulation Results

Friday April 25 2025 17:33:44 UTC

GitHub Revision: f7f0ea6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.290s	19.963us	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.680s	16.483us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	1.820s	47.685us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.980s	286.237us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.890s	79.457us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.870s	42.832us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.820s	47.685us	20	20	100.00
		rv_timer_csr_aliasing	1.890s	79.457us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	20.670s	9.353ms	50	50	100.00
V2	disabled	rv_timer_disabled	5.771m	217.612ms	48	50	96.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	18.689m	2.651s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	18.689m	2.651s	50	50	100.00
V2	stress	rv_timer_stress_all	14.577m	940.277ms	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.040s	23.401us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.490s	94.989us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.490s	94.989us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.680s	16.483us	5	5	100.00
		rv_timer_csr_rw	1.820s	47.685us	20	20	100.00
		rv_timer_csr_aliasing	1.890s	79.457us	5	5	100.00
		rv_timer_same_csr_outstanding	2.070s	126.668us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.680s	16.483us	5	5	100.00
		rv_timer_csr_rw	1.820s	47.685us	20	20	100.00
		rv_timer_csr_aliasing	1.890s	79.457us	5	5	100.00
		rv_timer_same_csr_outstanding	2.070s	126.668us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	rv_timer_sec_cm	2.300s	96.717us	5	5	100.00
		rv_timer_tl_intg_err	2.720s	126.421us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.720s	126.421us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.180m	13.112ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			618	620	99.68

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
91.74	99.65	99.08	92.06	--	99.13	99.68	60.86

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
  • Test rv_timer_disabled has 2 failures.

    • 33.rv_timer_disabled.73515931593542004655909603884494414019349049743114376514962131025296976184108
      Line 75, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/33.rv_timer_disabled/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 47.rv_timer_disabled.53767018895691901153558760791977821337069349858289141163504413332555468879801
      Line 75, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/47.rv_timer_disabled/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---