SPI_DEVICE/1R1W Simulation Results

Friday April 25 2025 17:33:44 UTC

GitHub Revision: f7f0ea6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	5.242m	184.815ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.810s	108.000us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	4.340s	181.703us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	28.210s	6.689ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	20.100s	4.510ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.270s	495.022us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	4.340s	181.703us	20	20	100.00
		spi_device_csr_aliasing	20.100s	4.510ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.360s	63.341us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.840s	61.671us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.330s	39.136us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.290s	1.621us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	2.200s	5.553us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	5.460s	163.297us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	5.460s	163.297us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.500s	8.268ms	50	50	100.00
		spi_device_tpm_sts_read	2.730s	107.546us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	49.010s	8.075ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	23.750s	6.227ms	50	50	100.00
		spi_device_flash_all	4.546m	54.475ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	31.870s	44.406ms	50	50	100.00
		spi_device_flash_all	4.546m	54.475ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	31.870s	44.406ms	50	50	100.00
		spi_device_flash_all	4.546m	54.475ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	4.546m	54.475ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	27.120s	16.638ms	50	50	100.00
		spi_device_flash_all	4.546m	54.475ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	27.120s	16.638ms	50	50	100.00
		spi_device_flash_all	4.546m	54.475ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	27.120s	16.638ms	50	50	100.00
		spi_device_flash_all	4.546m	54.475ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	27.120s	16.638ms	50	50	100.00
		spi_device_flash_all	4.546m	54.475ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	27.120s	16.638ms	50	50	100.00
		spi_device_flash_all	4.546m	54.475ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	36.080s	10.198ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.433m	39.470ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.433m	39.470ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.433m	39.470ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	37.120s	5.468ms	50	50	100.00
		spi_device_read_buffer_direct	21.990s	7.643ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.433m	39.470ms	50	50	100.00
		spi_device_flash_all	4.546m	54.475ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	4.546m	54.475ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	4.546m	54.475ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	25.660s	3.867ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	25.660s	3.867ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	5.242m	184.815ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	7.925m	216.360ms	50	50	100.00
V2	stress_all	spi_device_stress_all	13.124m	117.998ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.380s	95.226us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.540s	66.946us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.550s	316.755us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.550s	316.755us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.810s	108.000us	5	5	100.00
		spi_device_csr_rw	4.340s	181.703us	20	20	100.00
		spi_device_csr_aliasing	20.100s	4.510ms	5	5	100.00
		spi_device_same_csr_outstanding	5.170s	177.735us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.810s	108.000us	5	5	100.00
		spi_device_csr_rw	4.340s	181.703us	20	20	100.00
		spi_device_csr_aliasing	20.100s	4.510ms	5	5	100.00
		spi_device_same_csr_outstanding	5.170s	177.735us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	2.810s	541.937us	5	5	100.00
		spi_device_tl_intg_err	20.270s	2.068ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	20.270s	2.068ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	3.544m	138.877ms	50	50	100.00
		TOTAL			1130	1151	98.18

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.44	98.98	96.23	83.25	89.36	98.37	95.66	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:
  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.18172398596170523364756174284545950115758648914914503049668864856538228138781
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   3870136 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[63])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3870136 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   3870136 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[959])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.10134784072574318570430785867925162812690213325273201650472967486957954864517
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1374575 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[54])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1374575 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1374575 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[950])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.98085116947838995032317434867016294285190384761639103594813007492328485223832
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   5035568 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   5035568 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   5116568 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcb0605 [110010110000011000000101] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   5116568 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0xcb0605 [110010110000011000000101] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])