SPI_HOST Simulation Results

Friday April 25 2025 17:33:44 UTC

GitHub Revision: f7f0ea6

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	6.467m	63.720ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	20.516us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	20.989us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	7.000s	924.422us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	34.038us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	130.546us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	20.989us	20	20	100.00
		spi_host_csr_aliasing	5.000s	34.038us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	5.000s	43.099us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	15.738us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	6.000s	57.982us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.967m	18.374ms	50	50	100.00
		spi_host_error_cmd	5.000s	25.212us	50	50	100.00
		spi_host_event	14.700m	109.872ms	50	50	100.00
V2	clock_rate	spi_host_speed	28.000s	5.552ms	49	50	98.00
V2	speed	spi_host_speed	28.000s	5.552ms	49	50	98.00
V2	chip_select_timing	spi_host_speed	28.000s	5.552ms	49	50	98.00
V2	sw_reset	spi_host_sw_reset	3.850m	6.859ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	6.000s	272.467us	50	50	100.00
V2	cpol_cpha	spi_host_speed	28.000s	5.552ms	49	50	98.00
V2	full_cycle	spi_host_speed	28.000s	5.552ms	49	50	98.00
V2	duplex	spi_host_smoke	6.467m	63.720ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	6.467m	63.720ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.883m	9.318ms	50	50	100.00
V2	spien	spi_host_spien	2.733m	13.333ms	50	50	100.00
V2	stall	spi_host_status_stall	13.417m	22.794ms	45	50	90.00
V2	Idlecsbactive	spi_host_idlecsbactive	50.000s	1.866ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	2.967m	18.374ms	50	50	100.00
V2	alert_test	spi_host_alert_test	5.000s	19.433us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	15.802us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	7.000s	499.885us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	7.000s	499.885us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	20.516us	5	5	100.00
		spi_host_csr_rw	5.000s	20.989us	20	20	100.00
		spi_host_csr_aliasing	5.000s	34.038us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	99.010us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	20.516us	5	5	100.00
		spi_host_csr_rw	5.000s	20.989us	20	20	100.00
		spi_host_csr_aliasing	5.000s	34.038us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	99.010us	20	20	100.00
V2		TOTAL			684	690	99.13
V2S	tl_intg_err	spi_host_tl_intg_err	6.000s	184.416us	20	20	100.00
		spi_host_sec_cm	5.000s	69.820us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	6.000s	184.416us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	47.400m	100.003ms	1	10	10.00
		TOTAL			825	840	98.21

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.26	96.74	93.21	98.69	94.40	88.02	100.00	96.86	91.56

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 4 failures:

  • Test spi_host_upper_range_clkdiv has 4 failures.

    • 1.spi_host_upper_range_clkdiv.47209211165756466985271630255640781089444433656936214695828393885156016840812
      Line 129, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100003177226 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x4a0e4bd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100003177226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.spi_host_upper_range_clkdiv.48164620008391807321797517726677131637376572179565452453868597652192323426465
      Line 182, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100005572520 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xda008b54, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100005572520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Job timed out after * minutes has 3 failures:

  • Test spi_host_upper_range_clkdiv has 3 failures.

    • 3.spi_host_upper_range_clkdiv.93118741994289461606288982458491960531259210700641907857483921878030935421129
      Log /nightly/runs/scratch/master/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log

        Job timed out after 60 minutes
      

    • 4.spi_host_upper_range_clkdiv.110453446844064886719924117940974453875674314723370137397365991599299019830577
      Log /nightly/runs/scratch/master/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log

        Job timed out after 60 minutes
      

    • ... and 1 more failures.

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=78) has 3 failures:

  • Test spi_host_status_stall has 3 failures.

    • 24.spi_host_status_stall.17555354987558044762972479443352188790231936487057190698027701921575046312403
      Line 674, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/24.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 22794043204 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x123dcd14, Comparison=CompareOpEq, exp_data=0x1, call_count=78)
        UVM_INFO @ 22794043204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 45.spi_host_status_stall.106600111840762979631898578909151480016589758691221256061905976365733682174990
      Line 686, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/45.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 10184204033 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xd4d05f14, Comparison=CompareOpEq, exp_data=0x1, call_count=78)
        UVM_INFO @ 10184204033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 2.spi_host_upper_range_clkdiv.32713717957941625003296661292779319621587255829463844718941419361983306396591
      Line 212, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:

  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 8.spi_host_upper_range_clkdiv.10989154036463830189379003675192324004998981185250680779656180302808501984410
      Line 145, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100002899200 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x717efad4, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
        UVM_INFO @ 100002899200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=90) has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 38.spi_host_status_stall.3244505712113103390373839724759324198099026041985656723700874206585553740252
      Line 762, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/38.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 11869779654 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x46b43e54, Comparison=CompareOpEq, exp_data=0x1, call_count=90)
        UVM_INFO @ 11869779654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=173) has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 40.spi_host_status_stall.92961019975784525603980198149603979726598207932607723696826874313168176022682
      Line 843, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/40.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 17112047223 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3c8cd054, Comparison=CompareOpEq, exp_data=0x0, call_count=173)
        UVM_INFO @ 17112047223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=146) has 1 failures:

  • Test spi_host_speed has 1 failures.

    • 42.spi_host_speed.73904271411128950484695023224292424783114367798044704647858179735246664494446
      Line 787, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/42.spi_host_speed/latest/run.log

        UVM_FATAL @ 10197367797 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0xc0575d14, Comparison=CompareOpEq, exp_data=0x0, call_count=146)
        UVM_INFO @ 10197367797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---