SRAM_CTRL/MAIN Simulation Results

Friday April 25 2025 17:33:44 UTC

GitHub Revision: f7f0ea6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.661m	2.757ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.100s	35.814us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.210s	33.607us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.630s	840.747us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.140s	16.238us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	6.970s	1.524ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.210s	33.607us	20	20	100.00
		sram_ctrl_csr_aliasing	2.140s	16.238us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.333m	82.702ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.828m	14.268ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	21.318m	88.814ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	5.857m	27.018ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	41.989m	176.029ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	18.636m	83.923ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.147m	85.988ms	50	50	100.00
V2	executable	sram_ctrl_executable	25.431m	34.053ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.487m	2.157ms	50	50	100.00
		sram_ctrl_partial_access_b2b	8.931m	58.560ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.832m	3.053ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.716m	8.661ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.785m	3.799ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	19.112m	35.906ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	7.160s	3.736ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.197h	1.590s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.600s	16.858us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.980s	177.494us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.980s	177.494us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.100s	35.814us	5	5	100.00
		sram_ctrl_csr_rw	2.210s	33.607us	20	20	100.00
		sram_ctrl_csr_aliasing	2.140s	16.238us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.200s	25.005us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.100s	35.814us	5	5	100.00
		sram_ctrl_csr_rw	2.210s	33.607us	20	20	100.00
		sram_ctrl_csr_aliasing	2.140s	16.238us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.200s	25.005us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.203m	7.206ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.590s	34.877us	0	5	0.00
		sram_ctrl_tl_intg_err	4.460s	341.189us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.590s	34.877us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.460s	341.189us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	19.112m	35.906ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	19.112m	35.906ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.210s	33.607us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	25.431m	34.053ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	25.431m	34.053ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	25.431m	34.053ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.147m	85.988ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	12.460s	7.383ms	43	50	86.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.203m	7.206ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	10.190s	2.638ms	40	50	80.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.661m	2.757ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.661m	2.757ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	25.431m	34.053ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.590s	34.877us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.147m	85.988ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.590s	34.877us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.590s	34.877us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.661m	2.757ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.590s	34.877us	0	5	0.00
V2S		TOTAL			123	145	84.83
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.508m	42.467ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1168	1190	98.15

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	99.29	93.01	85.18	100.00	98.07	98.59	98.14

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 10 failures:
  • Test sram_ctrl_readback_err has 10 failures.

    • 3.sram_ctrl_readback_err.96031671041121596953334880475342411642914590999207190449198505926910358206984
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 684947057 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x3b) != exp (0x2d)
        UVM_INFO @ 684947057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.sram_ctrl_readback_err.84115927417272136567157868632540054815397715676132959571321931743827068250875
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/5.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 734377556 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x3c) != exp (0x64)
        UVM_INFO @ 734377556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• Offending 'reqfifo_rvalid' has 7 failures:
  • Test sram_ctrl_mubi_enc_err has 7 failures.

    • 0.sram_ctrl_mubi_enc_err.51332983575131181963583068321110713589425291279994337989979630336225302858967
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2738985694 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2738985694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_mubi_enc_err.51319471902398955061196429873871747337356784169546795057466761685638011744442
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2531170378 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2531170378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 5 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 4 failures:
  • Test sram_ctrl_sec_cm has 4 failures.

    • 0.sram_ctrl_sec_cm.91891528817372321589102148781298919763287772502960761867525638718034313848566
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  34877206 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  34877206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.sram_ctrl_sec_cm.9407137746822656885516721460416530901247964777095078803140132278121444955094
      Line 97, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7940089 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7940089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• Offending '(depth_o <= *'(Depth))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 2.sram_ctrl_sec_cm.98584337991845419873081436024864961989241587194395263484668429583343135267604
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   1370141 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   1370141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---