SRAM_CTRL/RET Simulation Results

Friday April 25 2025 17:33:44 UTC

GitHub Revision: `f7f0ea6`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.415m	150.976us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.430s	22.173us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.420s	20.051us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.340s	129.355us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.390s	47.725us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.520s	40.435us	16	20	80.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.420s	20.051us	20	20	100.00
		sram_ctrl_csr_aliasing	2.390s	47.725us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.900s	711.183us	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	7.790s	201.013us	50	50	100.00
V1		TOTAL			201	205	98.05
V2	multiple_keys	sram_ctrl_multiple_keys	19.393m	20.621ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	5.984m	14.681ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.418m	21.557ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	22.299m	5.063ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	13.600s	1.561ms	50	50	100.00
V2	executable	sram_ctrl_executable	19.964m	17.241ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.818m	2.967ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.863m	28.457ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.424m	1.403ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.645m	617.107us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.863m	1.198ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	21.689m	23.224ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.550s	29.864us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.126h	199.523ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.230s	13.829us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.700s	42.020us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.700s	42.020us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.430s	22.173us	5	5	100.00
		sram_ctrl_csr_rw	2.420s	20.051us	20	20	100.00
		sram_ctrl_csr_aliasing	2.390s	47.725us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.710s	14.593us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.430s	22.173us	5	5	100.00
		sram_ctrl_csr_rw	2.420s	20.051us	20	20	100.00
		sram_ctrl_csr_aliasing	2.390s	47.725us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.710s	14.593us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.830s	503.293us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.130s	7.560us	0	5	0.00
		sram_ctrl_tl_intg_err	4.670s	1.548ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.130s	7.560us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.670s	1.548ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	21.689m	23.224ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	21.689m	23.224ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.420s	20.051us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	19.964m	17.241ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	19.964m	17.241ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	19.964m	17.241ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	13.600s	1.561ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.850s	494.897us	44	50	88.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.830s	503.293us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.710s	124.051us	40	50	80.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.415m	150.976us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.415m	150.976us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	19.964m	17.241ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.130s	7.560us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	13.600s	1.561ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.130s	7.560us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.130s	7.560us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.415m	150.976us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.130s	7.560us	0	5	0.00
V2S		TOTAL			124	145	85.52
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	7.722m	1.486ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1164	1190	97.82

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	99.26	93.01	85.10	100.00	98.03	98.58	98.33

Failure Buckets

UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 10 failures:
- Test sram_ctrl_readback_err has 10 failures.
  - 3.sram_ctrl_readback_err.94135988667880518572330964615131147722633557272802527082920960246507761196806
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  29517806 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x13) != exp (0x5b)
  UVM_INFO @  29517806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.sram_ctrl_readback_err.44157286820807846625747556513841101042980850918137042041999620355994326546272
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  26535230 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x67) != exp (0x46)
  UVM_INFO @  26535230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.
Offending 'reqfifo_rvalid' has 6 failures:
- Test sram_ctrl_mubi_enc_err has 6 failures.
  - 10.sram_ctrl_mubi_enc_err.41138204669030939350890911527140513315191948188226600295899185287915291611422
    Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @  99096921 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @  99096921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 27.sram_ctrl_mubi_enc_err.96813408673944991665344806620482321881095988048145683774513934339960496775366
    Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/27.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 271764442 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 271764442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

Test sram_ctrl_sec_cm has 2 failures.

0.sram_ctrl_sec_cm.74872866449276097721657773122191409960670341274119044089199355499497743450243
Line 103, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @   7560287 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   7560287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.sram_ctrl_sec_cm.44956941170909388768403501974516596079967635518085998540922441698173577178840
Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @   7098867 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   7098867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 1.sram_ctrl_csr_mem_rw_with_rand_reset.88211374931711018895354645692096596041749268144563418908515563751162543823588
    Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  30908614 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  30908614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 19.sram_ctrl_csr_mem_rw_with_rand_reset.115242967522598330511513736515767141569439597717080864567542155075268736525584
    Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/19.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  68883582 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (15 [0xf] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  68883582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(!$isunknown(rdata_o))' has 2 failures:

Test sram_ctrl_sec_cm has 2 failures.

2.sram_ctrl_sec_cm.68201712692051816184757424904291941616368381399573948360967255074359291247333
Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   1862350 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   1862350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.sram_ctrl_sec_cm.30640514435183638644627688866240309279628363424586464442554846818039747256967
Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   2173095 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   2173095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 0.sram_ctrl_csr_mem_rw_with_rand_reset.82688075999420779348723488539063660996769536326477253089031745326301767393414
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 154217030 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @ 154217030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(depth_o <= *'(Depth))' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 1.sram_ctrl_sec_cm.12761692748949704187270506767149080457078512050096220757679126683240955903485
    Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(depth_o <= 2'(Depth))'
  UVM_ERROR @   4083801 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
  UVM_INFO @   4083801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 2.sram_ctrl_csr_mem_rw_with_rand_reset.44988839361609966593893254826632068786046342127291350910231787403242838146715
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  49173496 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (13 [0xd] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  49173496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:928) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 15.sram_ctrl_stress_all_with_rand_reset.80540558086853371994544722827741548086380577405070124358019790233765816889668
    Line 307, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/15.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5907842460 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5907842460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```