UART Simulation Results

Friday April 25 2025 17:33:44 UTC

GitHub Revision: `f7f0ea6`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	20.250s	5.385ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.280s	20.675us	5	5	100.00
V1	csr_rw	uart_csr_rw	2.340s	26.353us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.640s	175.763us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	2.480s	111.139us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.880s	33.171us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	2.340s	26.353us	20	20	100.00
		uart_csr_aliasing	2.480s	111.139us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	2.925m	132.640ms	50	50	100.00
V2	parity	uart_smoke	20.250s	5.385ms	50	50	100.00
		uart_tx_rx	2.925m	132.640ms	50	50	100.00
V2	parity_error	uart_intr	5.861m	369.106ms	50	50	100.00
		uart_rx_parity_err	4.676m	133.135ms	50	50	100.00
V2	watermark	uart_tx_rx	2.925m	132.640ms	50	50	100.00
		uart_intr	5.861m	369.106ms	50	50	100.00
V2	fifo_full	uart_fifo_full	8.726m	166.233ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	4.223m	126.861ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	15.331m	158.953ms	300	300	100.00
V2	rx_frame_err	uart_intr	5.861m	369.106ms	50	50	100.00
V2	rx_break_err	uart_intr	5.861m	369.106ms	50	50	100.00
V2	rx_timeout	uart_intr	5.861m	369.106ms	50	50	100.00
V2	perf	uart_perf	20.691m	24.564ms	50	50	100.00
V2	sys_loopback	uart_loopback	33.230s	11.841ms	50	50	100.00
V2	line_loopback	uart_loopback	33.230s	11.841ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	3.581m	205.413ms	48	50	96.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.144m	73.663ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	24.600s	6.250ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.127m	7.597ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	14.792m	120.256ms	50	50	100.00
V2	stress_all	uart_stress_all	39.977m	334.900ms	50	50	100.00
V2	alert_test	uart_alert_test	2.200s	24.110us	50	50	100.00
V2	intr_test	uart_intr_test	2.340s	15.505us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.480s	108.895us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.480s	108.895us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.280s	20.675us	5	5	100.00
		uart_csr_rw	2.340s	26.353us	20	20	100.00
		uart_csr_aliasing	2.480s	111.139us	5	5	100.00
		uart_same_csr_outstanding	2.340s	43.119us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.280s	20.675us	5	5	100.00
		uart_csr_rw	2.340s	26.353us	20	20	100.00
		uart_csr_aliasing	2.480s	111.139us	5	5	100.00
		uart_same_csr_outstanding	2.340s	43.119us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	2.480s	512.036us	5	5	100.00
		uart_tl_intg_err	3.120s	518.341us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	3.120s	518.341us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.795m	7.687ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1317	1320	99.77

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.76	99.17	98.25	91.55	--	98.15	100.00	99.44

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 1 failures:

Test uart_noise_filter has 1 failures.

16.uart_noise_filter.40718765462135282108854811741229920161567960580987219171983283585585783965632
Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/16.uart_noise_filter/latest/run.log

  UVM_ERROR @   8988369 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
  UVM_INFO @ 13372470276 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 1/14
  UVM_INFO @ 14786981592 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 2/14
  UVM_INFO @ 15560987784 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 3/14
  UVM_INFO @ 17605462473 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 4/14

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_noise_filter has 1 failures.
  - 21.uart_noise_filter.109171915440813440164058507801598891629481936699756477040396152443386537274013
    Line 80, in log /nightly/runs/scratch/master/uart-sim-vcs/21.uart_noise_filter/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:832) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

94.uart_stress_all_with_rand_reset.88076206249867738881509265179345639276635212205514011810562547191359778942013
Line 171, in log /nightly/runs/scratch/master/uart-sim-vcs/94.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 13773931173 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 13773931173 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 6/10
  UVM_INFO @ 13774385723 ps: (cip_base_vseq.sv:856) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 6/10