CHIP Simulation Results

Friday April 25 2025 17:33:44 UTC

GitHub Revision: `f7f0ea6`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.756m		0	5	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.756m		0	5	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	2.248m		0	20	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	2.225m		0	5	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	2.195m		0	5	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.271m	5.727ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.271m	5.727ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.271m	5.727ms	3	3	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	1.747m		0	3	0.00
		chip_sw_example_manufacturer	3.036m		0	3	0.00
		chip_sw_example_concurrency	5.112m	5.455ms	3	3	100.00
		chip_sw_uart_smoketest_signed	19.688s		0	3	0.00
V1	csr_bit_bash	chip_csr_bit_bash	15.090s		0	3	0.00
V1	csr_aliasing	chip_csr_aliasing	18.690s		0	3	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	18.690s		0	3	0.00
V1	xbar_smoke	xbar_smoke	35.550s	66.498us	100	100	100.00
V1		TOTAL			106	156	67.95
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	2.708m		0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	15.682m	8.288ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	6.621m	5.745ms	0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.606m		0	3	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	1.813m		0	3	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	2.626m		0	3	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.909m		0	3	0.00
V2	chip_pin_mux	chip_padctrl_attributes	5.360s		0	10	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.360s		0	10	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.924m		0	3	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	3.090m		0	3	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.975m		0	6	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.975m		0	6	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	4.355m	4.226ms	0	3	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	4.569m	3.510ms	0	3	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	8.655m	15.446ms	0	3	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	18.882s		0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	17.147s		0	3	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	22.279m	27.504ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	8.247m	6.465ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	30.977m	18.015ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	30.977m	18.015ms	0	3	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	23.228s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	18.774s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	18.774s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	26.291s		0	5	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.565m	3.906ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	7.030m	4.658ms	3	3	100.00
		chip_sw_aes_idle	5.729m	4.959ms	3	3	100.00
		chip_sw_hmac_enc_idle	6.649m	6.041ms	3	3	100.00
		chip_sw_kmac_idle	4.850m	3.489ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	17.774s		0	3	0.00
		chip_sw_clkmgr_off_hmac_trans	21.945s		0	3	0.00
		chip_sw_clkmgr_off_kmac_trans	28.864s		0	3	0.00
		chip_sw_clkmgr_off_otbn_trans	15.987s		0	3	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	17.401s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.821s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	18.316s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.958s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	18.090s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	18.148s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	17.093s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	17.401s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.821s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	18.316s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.958s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	18.090s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	18.148s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	17.093s		0	3	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	18.695s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.472m	10.340us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.177m	10.280us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.189m	10.320us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.125m	10.180us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.987s		0	3	0.00
		chip_sw_clkmgr_jitter	4.635m	4.749ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	5.452m	5.102ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	18.103s		0	3	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	1.129m	10.220us	0	3	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	55.910s	10.240us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	1.384m	10.240us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	1.537m	10.200us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	59.090s	10.240us	0	3	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	23.002s		0	3	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	16.422s		0	3	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	18.328s		0	3	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	19.844s		0	3	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	34.803m	15.959ms	98	100	98.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	14.153m	15.309ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	18.774s		0	3	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	22.721s		0	3	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	14.153m	15.309ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	21.859s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	40.370s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	39.731s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	22.470s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	34.175s		0	3	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	34.803m	15.959ms	98	100	98.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	8.655m	15.446ms	0	3	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	34.863m	20.016ms	0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	9.486m	9.175ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	14.096m	30.016ms	0	3	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	6.256m	5.879ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	34.803m	15.959ms	98	100	98.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	20.449s		0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	18.039s		0	3	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	34.803m	15.959ms	98	100	98.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	16.974s		0	3	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	14.096m	30.016ms	0	3	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	17.445s		0	3	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	18.409s		0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	18.264s		0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	19.655s		0	3	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	18.093s		0	3	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	17.303s		0	3	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	18.039s		0	3	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	18.966s		0	15	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	20.278s		0	3	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	18.966s		0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	18.966s		0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	18.966s		0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	9.778m	8.494ms	0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	19.078s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	20.583s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	20.643s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	18.405s		0	3	0.00
		chip_sw_lc_ctrl_transition	18.966s		0	15	0.00
		chip_sw_keymgr_dpe_key_derivation	9.485m	7.226ms	0	3	0.00
		chip_sw_rom_ctrl_integrity_check	12.466m	11.577ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	19.679s		0	3	0.00
		chip_prim_tl_access	33.781m	27.345ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	17.401s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.821s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	18.316s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	18.958s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	18.090s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	18.148s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	17.093s		0	3	0.00
		chip_rv_dm_lc_disabled	22.279m	27.504ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.975m	3.952ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	1.472m	10.340us	0	3	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.397m	4.161ms	3	3	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.729m	4.959ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	6.739m	5.878ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	1.177m	10.280us	0	3	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.649m	6.041ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.190m	3.640ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.894m	4.975ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	1.125m	10.180us	0	3	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	9.485m	7.226ms	0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	18.966s		0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	52.580s	10.160us	0	3	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	7.654m	4.869ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.850m	3.489ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	29.467s		0	3	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	29.467s		0	3	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	19.301s		0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.082m	4.407ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	16.275s		0	3	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	9.485m	7.226ms	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.189m	10.320us	0	3	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	17.294s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	18.695s		0	3	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	7.030m	4.658ms	3	3	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	7.030m	4.658ms	3	3	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	7.030m	4.658ms	3	3	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	10.102m	5.860ms	3	3	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	12.466m	11.577ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	12.466m	11.577ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	11.384m	10.324ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.987s		0	3	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	19.679s		0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	34.803m	15.959ms	98	100	98.00
		chip_sw_data_integrity_escalation	2.975m		0	6	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	18.966s		0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	10.102m	5.860ms	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	9.485m	7.226ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	11.384m	10.324ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	6.254m	5.997ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	10.102m	5.860ms	3	3	100.00
		chip_sw_keymgr_dpe_key_derivation	9.485m	7.226ms	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	11.384m	10.324ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	6.254m	5.997ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	18.966s		0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	17.934s		0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	20.278s		0	3	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	19.078s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	20.583s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	20.643s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	18.405s		0	3	0.00
		chip_sw_lc_ctrl_transition	18.966s		0	15	0.00
		chip_prim_tl_access	33.781m	27.345ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	33.781m	27.345ms	3	3	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	15.427s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	16.027s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	16.422s		0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	18.695s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.472m	10.340us	0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.177m	10.280us	0	3	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	1.189m	10.320us	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	1.125m	10.180us	0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	14.987s		0	3	0.00
		chip_sw_clkmgr_jitter	4.635m	4.749ms	3	3	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	10.586m	9.113ms	3	3	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	10.586m	9.113ms	3	3	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	7.026m	5.932ms	0	3	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	6.475m	5.737ms	3	3	100.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	5.657m	5.879ms	3	3	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	10.004m	5.933ms	0	3	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.445m	5.276ms	3	3	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	6.302m	5.801ms	3	3	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	6.254m	5.997ms	3	3	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	34.863m	20.016ms	0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	34.863m	20.016ms	0	3	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	5.647m	4.105ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.381m	4.410ms	3	3	100.00
		chip_sw_clkmgr_smoketest	6.043m	5.396ms	3	3	100.00
		chip_sw_csrng_smoketest	6.034m	4.694ms	3	3	100.00
		chip_sw_gpio_smoketest	6.222m	4.111ms	3	3	100.00
		chip_sw_hmac_smoketest	6.848m	4.516ms	3	3	100.00
		chip_sw_kmac_smoketest	6.823m	4.279ms	3	3	100.00
		chip_sw_otbn_smoketest	9.337m	6.451ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.616m	3.528ms	3	3	100.00
		chip_sw_rv_plic_smoketest	6.149m	4.403ms	3	3	100.00
		chip_sw_rv_timer_smoketest	7.150m	5.079ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.517m	4.476ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	5.448m	4.844ms	3	3	100.00
		chip_sw_uart_smoketest	6.275m	5.187ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	22.736s		0	3	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	19.688s		0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.708m		0	3	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	19.102s		0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	6.715m	5.754ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.591m	6.264ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.763m	4.595ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	5.001m	3.846ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	18.252s		0	3	0.00
		chip_rv_dm_lc_disabled	22.279m	27.504ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	18.804s		0	3	0.00
		chip_sw_lc_walkthrough_prod	18.876s		0	3	0.00
		chip_sw_lc_walkthrough_prodend	17.736s		0	3	0.00
		chip_sw_lc_walkthrough_rma	16.732s		0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	18.252s		0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	35.244s		0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	17.235s		0	3	0.00
		rom_volatile_raw_unlock	29.452s		0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	21.735s		0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.397m		0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.284m		0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	6.884m	5.460ms	0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors	6.884m	5.460ms	0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	18.690s		0	3	0.00
		chip_same_csr_outstanding	18.420s		0	3	0.00
V2	tl_d_partial_access	chip_csr_aliasing	18.690s		0	3	0.00
		chip_same_csr_outstanding	18.420s		0	3	0.00
V2	xbar_base_random_sequence	xbar_random	4.516m	533.200us	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	16.170s	13.677us	100	100	100.00
		xbar_smoke_large_delays	9.820m	2.664ms	100	100	100.00
		xbar_smoke_slow_rsp	10.525m	2.220ms	100	100	100.00
		xbar_random_zero_delays	2.124m	79.358us	100	100	100.00
		xbar_random_large_delays	42.162m	12.217ms	100	100	100.00
		xbar_random_slow_rsp	52.694m	14.225ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	2.919m	241.184us	100	100	100.00
		xbar_error_and_unmapped_addr	2.571m	212.907us	100	100	100.00
V2	xbar_error_cases	xbar_error_random	4.500m	492.974us	100	100	100.00
		xbar_error_and_unmapped_addr	2.571m	212.907us	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	8.153m	814.625us	100	100	100.00
		xbar_access_same_device_slow_rsp	58.885m	18.637ms	73	100	73.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	4.165m	483.752us	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	26.607m	3.546ms	100	100	100.00
		xbar_stress_all_with_error	39.939m	5.348ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	49.189m	5.962ms	99	100	99.00
		xbar_stress_all_with_reset_error	48.764m	5.971ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	18.313s		0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	16.778s		0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	17.876s		0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	14.873s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	17.392s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.260s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.604s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	12.759s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	19.169s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	14.264s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	15.041s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.151s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	14.912s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	15.263s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	16.719s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.938s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	17.878s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	17.646s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	16.202s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	15.871s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	16.047s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	17.444s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	14.801s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	17.264s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	18.334s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	18.006s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	16.733s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	18.525s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.541s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	18.046s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.820s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	18.151s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	15.834s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	17.247s		0	3	0.00
		rom_e2e_asm_init_dev	17.676s		0	3	0.00
		rom_e2e_asm_init_prod	17.359s		0	3	0.00
		rom_e2e_asm_init_prod_end	18.395s		0	3	0.00
		rom_e2e_asm_init_rma	17.248s		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	17.875s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	14.931s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	18.463s		0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	17.987s		0	3	0.00
V2		TOTAL			1908	2429	78.55
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	7.093m	4.244ms	3	3	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	5.079m	5.121ms	3	3	100.00
V2S		TOTAL			6	6	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	17.257s		0	1	0.00
		rom_e2e_jtag_debug_dev	14.458s		0	1	0.00
		rom_e2e_jtag_debug_rma	15.815s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	18.899s		0	3	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	34.803m	15.959ms	98	100	98.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	22.699s		0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	25.937m	16.847ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	18.359s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	19.053s		0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	17.257s		0	1	0.00
		rom_e2e_jtag_debug_dev	14.458s		0	1	0.00
		rom_e2e_jtag_debug_rma	15.815s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	16.547s		0	1	0.00
		rom_e2e_jtag_inject_dev	15.328s		0	1	0.00
		rom_e2e_jtag_inject_rma	13.017s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.473m		0	3	0.00
V3		TOTAL			1	20	5.00
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	28.617m	14.172ms	3	3	100.00
		chip_plic_all_irqs_0	13.678m	7.387ms	3	3	100.00
		chip_plic_all_irqs_10	14.995m	7.030ms	3	3	100.00
		chip_sw_dma_inline_hashing	7.261m	4.826ms	3	3	100.00
		chip_sw_dma_abort	6.329m	4.606ms	0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	17.703s		0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	17.766s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	17.958s		0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	17.933s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	18.796s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	18.404s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	18.193s		0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	22.122s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	18.332s		0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	20.093s		0	3	0.00
		chip_sw_mbx_smoketest	8.219m	4.254ms	3	3	100.00
		TOTAL			2036	2659	76.57

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
75.59	74.56	78.14	66.23	--	80.93	66.93	86.76

Failure Buckets

Job returned non-zero exit code has 478 failures:

Test chip_sw_example_rom has 3 failures.

0.chip_sw_example_rom.110182117033782363362842123098349420943319589097653869146411850057017348925252
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  Target //sw/device/tests:example_test_from_rom_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (293192)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (6d9be7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 78.038s, Critical Path: 0.07s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_example_rom.15426704277534717476346848854192522105420367231596479983093987736311391333595
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log

  DEBUG: /nightly/runs/opentitan/rules/autogen.bzl:452:14: NOTE: stamping is disabled, the chip_info section will use a fixed version string
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (bbf018)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (bb7416)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 6.158s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_example_manufacturer has 3 failures.

0.chip_sw_example_manufacturer.8468260821105149548369291018038158203055176275956259089155098220231059626293
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (aee670)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 157.192s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_example_manufacturer.56435538580096277057541904084171487331465577685922158643388058082125583085667
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (8fb416)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 4.199s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_data_integrity_escalation has 6 failures.

0.chip_sw_data_integrity_escalation.262630125523612062270643506495891119719065725054072928653490664900651962780
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (89d501)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 159.927s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_data_integrity_escalation.36760757304725796426280237357826644368588612567891372133157352230409391510544
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (113de3)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 1.804s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 4 more failures.

Test chip_sw_sleep_pin_wake has 3 failures.

0.chip_sw_sleep_pin_wake.31501591647680421464239536955152839337355670309699596731540398348191178082617
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (6aa7e5)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 156.753s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_sleep_pin_wake.47033521988292604540500034087085144097165904124399351224092538802525519040562
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (53b4c9)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 1.299s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test chip_sw_sleep_pin_retention has 3 failures.

0.chip_sw_sleep_pin_retention.103364662036252035927357397721043365514683658540065880928228740503882755349345
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (80305a)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 170.909s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_sleep_pin_retention.52381595258594823956199765132239885574198793092368753127520548223484160753061
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (72574f)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 8.317s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

... and 138 more tests.

Job timed out after * minutes has 28 failures:
- Test xbar_access_same_device_slow_rsp has 27 failures.
  - 2.xbar_access_same_device_slow_rsp.42469792870830125710427774651639285766837957989090680383122406667324845296373
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/2.xbar_access_same_device_slow_rsp/latest/run.log
```
  Job timed out after 60 minutes
```
  - 4.xbar_access_same_device_slow_rsp.8458548129466775805280383743263314097471928406650717118480495115068727604077
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/4.xbar_access_same_device_slow_rsp/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 25 more failures.
- Test xbar_stress_all_with_rand_reset has 1 failures.
  - 56.xbar_stress_all_with_rand_reset.85276949125980643792543637768754479813998683442561200671496611184751378070081
    Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/56.xbar_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 60 minutes
```
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 27 failures:
- Test chip_sw_aes_enc_jitter_en has 3 failures.
  - 0.chip_sw_aes_enc_jitter_en.76416905587434287734521706034817383925583409084825372461867982089488316661086
    Line 410, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aes_enc_jitter_en.70107986532925884702731851736803741701558507461126026858420606166822327151529
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_hmac_enc_jitter_en has 3 failures.
  - 0.chip_sw_hmac_enc_jitter_en.76152158810025785120843206894574869176394832752224553212553685360588208211831
    Line 434, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_hmac_enc_jitter_en.100019974748885092837237462095117895043305548782919605432132684540785658092243
    Line 454, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 3 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.51352237899893755015781699625891171351309565839336390633465229599997060234926
    Line 434, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_keymgr_dpe_key_derivation_jitter_en.17284582449992919697540816101231272999192646005362571253592271019552933842279
    Line 442, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_kmac_mode_kmac_jitter_en has 3 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.90905013224545389948686809559765847443826525113834398337261483375735286329739
    Line 409, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_kmac_mode_kmac_jitter_en.70268254919225061789156114378543063789800178519159499880388381453674823732747
    Line 449, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 3 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.65920586621240205986982984888716907567630022850334104786393285735793124711298
    Line 437, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_aes_enc_jitter_en_reduced_freq.101238877837647290177006629816777334307553267117684800445418943741438200064473
    Line 442, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- ... and 4 more tests.
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 12 failures:
- Test chip_tl_errors has 12 failures.
  - 0.chip_tl_errors.18887654537516480871225541340063190062698726587862287155146365488667684335043
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 5460.313256 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 5460.313256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_tl_errors.62688389020935674235186792598426581030417571609817044235044823605871762874858
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4403.982072 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4403.982072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 10 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 10 failures:
- Test chip_padctrl_attributes has 10 failures.
  - 0.chip_padctrl_attributes.10574189493180120744662888507407894733689879885878420676710761797467010257918
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 1.chip_padctrl_attributes.26743513853082318285296316407337179371811517716217591591477378521385567966560
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 8 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 9 failures:
- Test chip_csr_bit_bash has 3 failures.
  - 0.chip_csr_bit_bash.94972550264877738272978892007920973129392349460171265389483459554346192330102
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_bit_bash.22540849834018203058790578111890258919768801937567859771797791091292983693446
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_csr_aliasing has 3 failures.
  - 0.chip_csr_aliasing.112435472875621440140133794704618058336307035114898282963221590570284092344325
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_csr_aliasing.98182561934995169198413313315621436814687867565413344826697519081276667449227
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
- Test chip_same_csr_outstanding has 3 failures.
  - 0.chip_same_csr_outstanding.101210406964759742030303720060656566831048622699452567607173372461272141814454
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_same_csr_outstanding.98550261888294200905296057410238972715796419279289962834545661987748651899730
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 9 failures:

Test chip_sw_rstmgr_alert_info has 3 failures.

0.chip_sw_rstmgr_alert_info.55481942388986981295421360476713439118919663997955198284038941889438340333056
Line 477, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30015.572694 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30015.572694 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_rstmgr_alert_info.48837490714955979156088329467776438542357980038256182619002148748524316653607
Line 446, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30017.909326 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30017.909326 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_rstmgr_cpu_info has 3 failures.

0.chip_sw_rstmgr_cpu_info.68751393705128699969126989967454296749615782387753604954385014517692346159890
Line 523, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20015.629424 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20015.629424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_rstmgr_cpu_info.90395405545858511148866199686840117695939668622746448060956163780289268517880
Line 456, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20023.374658 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20023.374658 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_aon_timer_irq has 3 failures.

0.chip_sw_aon_timer_irq.81731440937504893848697496386613346595010914497275947940233333760679922414855
Line 457, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18025.871088 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18025.871088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_aon_timer_irq.63381529412283538820284508509402484263432600009885096588566554476519346573406
Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18015.829498 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18015.829498 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 6 failures:

Test chip_sw_keymgr_dpe_key_derivation has 3 failures.

0.chip_sw_keymgr_dpe_key_derivation.80756421977177975561817563909633094318367402616720509575074334912125617471154
Line 486, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8162.105088 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (10930301494524790635336771715457065425450636354048451370615179453614600591625 [0x182a54d752d6f83f2b2662e6239623a32b929817a3c8875ac4db93221f699909] vs 27805707889098441665903123602019276983781060737028262869977703942979996580547 [0x3d79791343bdefe67f25422ebf4bcc2ac09f4e3b5a46568ddfc02d9e10977ac3])
  UVM_INFO @ 8162.105088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_keymgr_dpe_key_derivation.72097704442169242600639485628135062278571913493785489115275538589777479949372
Line 488, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 7226.064576 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (4573851127250504962969735864180811716309051085707356104277220438277869602143 [0xa1cb53f55d3b5bc6075303411796acf379caf5a826f3cde46ed6cf68b85055f] vs 57957989110170402416209877032743689390256428842202265720496030509839556920717 [0x80230f30e3a1b9330db84bbd7a40cf0a83318c02f0005e3c578f035941b1c58d])
  UVM_INFO @ 7226.064576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_keymgr_dpe_key_derivation_prod has 3 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.23686835404713174503945951757778433469812568321658122551916805177994789237794
Line 482, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 8493.686680 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (57907201370057741455800833920535835530341242442533004881629617082244365260435 [0x80065082e8bce82b666495b9b22d8f6e3864521b5ce9693fb5d848219deb9693] vs 33660580086014906801338226661945249063306486082444537734884602907766107838129 [0x4a6b3692e853e6d8e9e4cbe6da1c1eeb8236598bc38c9fd46fbf37db2c3e96b1])
  UVM_INFO @ 8493.686680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_keymgr_dpe_key_derivation_prod.21860480792023776021881942089909381194530301673920660266400134529791579211441
Line 510, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 9878.825200 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (53752368306145607093545582209007836003798756802183809092205016943911648871274 [0x76d6c3275a099936acf220dd0be26f9d8e651dd23f2e4574a8b6329f0883c36a] vs 45274204991094405738433204186787127755818758087970081081534160990292307330774 [0x64184abc345a7434196998a635437075d84e1f3b9f4fd8af00e28afabd7bc6d6])
  UVM_INFO @ 9878.825200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 6 failures:

Test chip_jtag_csr_rw has 3 failures.

0.chip_jtag_csr_rw.82150035998284066184781968456719409633406548779009305853259144652713293237796
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4104.651087 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h9d2010d0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h20  a_opcode: 'h0  a_user: 'h2697c  d_param: 'h0  d_source: 'h20  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4104.651087 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_jtag_csr_rw.92918379517293904425997800545344597948915982243186428966003502620052085633023
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4226.422716 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hc71cd3f4  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3  a_opcode: 'h1  a_user: 'h248fc  d_param: 'h0  d_source: 'h3  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4226.422716 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_jtag_mem_access has 3 failures.

0.chip_jtag_mem_access.104797275621537197708201166126668897297231763816595095037346231424072020586822
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4451.624615 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hb0f88cef  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h1  a_user: 'h2489f  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4451.624615 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_jtag_mem_access.55157837388157398286140559356223221019938055809023912568627636355383142609527
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4850.004645 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hc086882b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h39  a_opcode: 'h1  a_user: 'h24894  d_param: 'h0  d_source: 'h39  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4850.004645 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 3 failures:
- Test chip_sw_spi_device_pass_through_collision has 3 failures.
  - 0.chip_sw_spi_device_pass_through_collision.18985926651901516072785793827680230430842501901734979650113872265510784180633
    Line 464, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4449.143910 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4449.143910 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_spi_device_pass_through_collision.71598119903265401312537400902336854186737821428691093424236896235669124754940
    Line 449, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5745.015640 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5745.015640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 3 failures:

Test chip_sw_soc_proxy_external_alerts has 3 failures.

0.chip_sw_soc_proxy_external_alerts.88797280238500901009436439773023593342886062954944132742147587881055892279047
Line 454, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log

  UVM_ERROR @ 5931.661182 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5931.661182 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_soc_proxy_external_alerts.39839264036924459770577993579713810171675269936671089222180745283350141394207
Line 414, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_soc_proxy_external_alerts/latest/run.log

  UVM_ERROR @ 4877.935880 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4877.935880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 3 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 3 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.45560617468527334076571742514514203304838839078421876507689909506751363409098
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5357.599060 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5357.599060 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_rv_core_ibex_nmi_irq.31636723193682253459974237845546391777183723731621159003468027926624854426314
    Line 419, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 4855.705244 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 4855.705244 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 3 failures:
- Test chip_sw_kmac_app_rom has 3 failures.
  - 0.chip_sw_kmac_app_rom.20089591571769789205320052627684690027631445210485158620278407131795335207770
    Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_kmac_app_rom.102056719029050564383622727987251377865372712506116927391144961912014641143812
    Line 449, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 3 failures:
- Test chip_rv_dm_ndm_reset_req has 3 failures.
  - 0.chip_rv_dm_ndm_reset_req.79886232861798479022499566500220966671826081740198769072951076339079832904232
    Line 403, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 15445.950184 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 15445.950184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_rv_dm_ndm_reset_req.53738670744258871661275143105297787439551145360027090861567430596514604527909
    Line 403, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 15529.945848 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 15529.945848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 3 failures:

Test chip_sw_dma_abort has 3 failures.

0.chip_sw_dma_abort.67697795304434968258607220509088077316307943667897402535856093897415525917193
Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 4871.604920 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4871.604920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_dma_abort.72728125563834140592439073473939420146900629192396610025748821091987012206051
Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/1.chip_sw_dma_abort/latest/run.log

  UVM_FATAL @ 4605.842856 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4605.842856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@37918) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures: