AES/MASKED Simulation Results

Friday May 02 2025 17:38:26 UTC

GitHub Revision: `c9ef9e5`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	6.000s	135.889us	1	1	100.00
V1	smoke	aes_smoke	20.000s	974.648us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	97.931us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	62.886us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	3.916ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	171.701us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	125.328us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	62.886us	20	20	100.00
		aes_csr_aliasing	6.000s	171.701us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	20.000s	974.648us	50	50	100.00
		aes_config_error	15.000s	767.336us	50	50	100.00
		aes_stress	52.000s	3.115ms	50	50	100.00
V2	key_length	aes_smoke	20.000s	974.648us	50	50	100.00
		aes_config_error	15.000s	767.336us	50	50	100.00
		aes_stress	52.000s	3.115ms	50	50	100.00
V2	back2back	aes_stress	52.000s	3.115ms	50	50	100.00
		aes_b2b	43.000s	906.226us	50	50	100.00
V2	backpressure	aes_stress	52.000s	3.115ms	50	50	100.00
V2	multi_message	aes_smoke	20.000s	974.648us	50	50	100.00
		aes_config_error	15.000s	767.336us	50	50	100.00
		aes_stress	52.000s	3.115ms	50	50	100.00
		aes_alert_reset	14.000s	697.230us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	128.533us	50	50	100.00
		aes_config_error	15.000s	767.336us	50	50	100.00
		aes_alert_reset	14.000s	697.230us	50	50	100.00
V2	trigger_clear_test	aes_clear	34.000s	2.447ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	224.271us	1	1	100.00
V2	reset_recovery	aes_alert_reset	14.000s	697.230us	50	50	100.00
V2	stress	aes_stress	52.000s	3.115ms	50	50	100.00
V2	sideload	aes_stress	52.000s	3.115ms	50	50	100.00
		aes_sideload	18.000s	1.370ms	50	50	100.00
V2	deinitialization	aes_deinit	11.000s	427.695us	50	50	100.00
V2	stress_all	aes_stress_all	6.550m	109.185ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	95.397us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	83.488us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	83.488us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	97.931us	5	5	100.00
		aes_csr_rw	5.000s	62.886us	20	20	100.00
		aes_csr_aliasing	6.000s	171.701us	5	5	100.00
		aes_same_csr_outstanding	6.000s	97.997us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	97.931us	5	5	100.00
		aes_csr_rw	5.000s	62.886us	20	20	100.00
		aes_csr_aliasing	6.000s	171.701us	5	5	100.00
		aes_same_csr_outstanding	6.000s	97.997us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	11.000s	424.058us	50	50	100.00
V2S	fault_inject	aes_fi	10.000s	407.599us	50	50	100.00
		aes_control_fi	44.000s	10.023ms	280	300	93.33
		aes_cipher_fi	46.000s	10.008ms	341	350	97.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	261.076us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	261.076us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	261.076us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	261.076us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	616.912us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	401.399us	5	5	100.00
		aes_tl_intg_err	7.000s	796.556us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	796.556us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	14.000s	697.230us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	261.076us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	20.000s	974.648us	50	50	100.00
		aes_stress	52.000s	3.115ms	50	50	100.00
		aes_alert_reset	14.000s	697.230us	50	50	100.00
		aes_core_fi	47.000s	10.083ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	261.076us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	754.905us	50	50	100.00
		aes_stress	52.000s	3.115ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	52.000s	3.115ms	50	50	100.00
		aes_sideload	18.000s	1.370ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	754.905us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	754.905us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	754.905us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	754.905us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	754.905us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	52.000s	3.115ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	52.000s	3.115ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	10.000s	407.599us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	10.000s	407.599us	50	50	100.00
		aes_control_fi	44.000s	10.023ms	280	300	93.33
		aes_cipher_fi	46.000s	10.008ms	341	350	97.43
		aes_ctr_fi	6.000s	55.131us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	10.000s	407.599us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	10.000s	407.599us	50	50	100.00
		aes_control_fi	44.000s	10.023ms	280	300	93.33
		aes_cipher_fi	46.000s	10.008ms	341	350	97.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	46.000s	10.008ms	341	350	97.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	10.000s	407.599us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	10.000s	407.599us	50	50	100.00
		aes_control_fi	44.000s	10.023ms	280	300	93.33
		aes_ctr_fi	6.000s	55.131us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	10.000s	407.599us	50	50	100.00
		aes_control_fi	44.000s	10.023ms	280	300	93.33
		aes_cipher_fi	46.000s	10.008ms	341	350	97.43
		aes_ctr_fi	6.000s	55.131us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	14.000s	697.230us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	10.000s	407.599us	50	50	100.00
		aes_control_fi	44.000s	10.023ms	280	300	93.33
		aes_cipher_fi	46.000s	10.008ms	341	350	97.43
		aes_ctr_fi	6.000s	55.131us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	10.000s	407.599us	50	50	100.00
		aes_control_fi	44.000s	10.023ms	280	300	93.33
		aes_cipher_fi	46.000s	10.008ms	341	350	97.43
		aes_ctr_fi	6.000s	55.131us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	10.000s	407.599us	50	50	100.00
		aes_control_fi	44.000s	10.023ms	280	300	93.33
		aes_ctr_fi	6.000s	55.131us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	10.000s	407.599us	50	50	100.00
		aes_control_fi	44.000s	10.023ms	280	300	93.33
		aes_cipher_fi	46.000s	10.008ms	341	350	97.43
V2S		TOTAL			954	985	96.85
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	29.000s	2.077ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1561	1602	97.44

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.42	98.63	96.52	99.44	95.68	98.07	97.78	98.96	99.20

Failure Buckets

Job timed out after * minutes has 15 failures:
- Test aes_control_fi has 15 failures.
  - 34.aes_control_fi.96885033452210507220951220242558544144004189006562359619393454047700556949935
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/34.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 42.aes_control_fi.97901426091176493081016223707946072333425028121977539784657227249676101774514
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/42.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 13 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 31.aes_cipher_fi.107459437541124945064548984903088038441898376382251267389622939444979782224138
    Line 138, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/31.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10019410975 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019410975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 64.aes_cipher_fi.40157767218390171939823537793546357882069470232768653361481369007141566821636
    Line 141, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/64.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006146687 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006146687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.68613556807811283620749774511696244090159130043776024198794483874927280535692
Line 611, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3234712801 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3234712801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.88658749898014082050475120417989269707056515575950412022211902584847307785434
Line 267, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  70526893 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  70526893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 44.aes_control_fi.112066528664394091750637322611378431814158197738791908202312708858559310190213
    Line 141, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/44.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006761874 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006761874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 52.aes_control_fi.24883329991125819453252599651480221440064218124628428414755896956503492372371
    Line 134, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/52.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10277177967 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10277177967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 16.aes_core_fi.112166091164401005282956305922734595299604917162590855905805306660344231287968
    Line 135, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/16.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006035718 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006035718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 66.aes_core_fi.8731015756389386262546825976970389943663750536009064054384314436109404950866
    Line 135, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/66.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10083445124 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10083445124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.90988859370574659666110565167166159164581338751199834104552475961975111664101
    Line 236, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 783388896 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 783388896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.89280570107225450102494195492457084595748862779733900050966756490596556860836
    Line 635, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1961386620 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1961386620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```