AES/UNMASKED Simulation Results

Friday May 02 2025 17:38:26 UTC

GitHub Revision: `c9ef9e5`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	65.032us	1	1	100.00
V1	smoke	aes_smoke	6.000s	175.691us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	7.000s	58.217us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	62.598us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	2.008ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	9.000s	143.681us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	88.618us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	62.598us	20	20	100.00
		aes_csr_aliasing	9.000s	143.681us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	175.691us	50	50	100.00
		aes_config_error	6.000s	344.553us	50	50	100.00
		aes_stress	7.000s	406.806us	50	50	100.00
V2	key_length	aes_smoke	6.000s	175.691us	50	50	100.00
		aes_config_error	6.000s	344.553us	50	50	100.00
		aes_stress	7.000s	406.806us	50	50	100.00
V2	back2back	aes_stress	7.000s	406.806us	50	50	100.00
		aes_b2b	10.000s	122.862us	50	50	100.00
V2	backpressure	aes_stress	7.000s	406.806us	50	50	100.00
V2	multi_message	aes_smoke	6.000s	175.691us	50	50	100.00
		aes_config_error	6.000s	344.553us	50	50	100.00
		aes_stress	7.000s	406.806us	50	50	100.00
		aes_alert_reset	7.000s	443.491us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	88.824us	50	50	100.00
		aes_config_error	6.000s	344.553us	50	50	100.00
		aes_alert_reset	7.000s	443.491us	50	50	100.00
V2	trigger_clear_test	aes_clear	8.000s	205.790us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	200.085us	1	1	100.00
V2	reset_recovery	aes_alert_reset	7.000s	443.491us	50	50	100.00
V2	stress	aes_stress	7.000s	406.806us	50	50	100.00
V2	sideload	aes_stress	7.000s	406.806us	50	50	100.00
		aes_sideload	9.000s	406.743us	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	84.823us	50	50	100.00
V2	stress_all	aes_stress_all	27.000s	2.303ms	10	10	100.00
V2	alert_test	aes_alert_test	5.000s	139.239us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	10.000s	239.476us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	10.000s	239.476us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	7.000s	58.217us	5	5	100.00
		aes_csr_rw	7.000s	62.598us	20	20	100.00
		aes_csr_aliasing	9.000s	143.681us	5	5	100.00
		aes_same_csr_outstanding	8.000s	171.357us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	7.000s	58.217us	5	5	100.00
		aes_csr_rw	7.000s	62.598us	20	20	100.00
		aes_csr_aliasing	9.000s	143.681us	5	5	100.00
		aes_same_csr_outstanding	8.000s	171.357us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	9.000s	515.972us	50	50	100.00
V2S	fault_inject	aes_fi	6.000s	287.501us	50	50	100.00
		aes_control_fi	45.000s	200.000ms	285	300	95.00
		aes_cipher_fi	31.000s	10.018ms	328	350	93.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	9.000s	115.317us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	9.000s	115.317us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	9.000s	115.317us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	9.000s	115.317us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	9.000s	259.689us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	1.476ms	5	5	100.00
		aes_tl_intg_err	8.000s	232.510us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	232.510us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	7.000s	443.491us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	9.000s	115.317us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	175.691us	50	50	100.00
		aes_stress	7.000s	406.806us	50	50	100.00
		aes_alert_reset	7.000s	443.491us	50	50	100.00
		aes_core_fi	4.400m	10.012ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	9.000s	115.317us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	116.470us	50	50	100.00
		aes_stress	7.000s	406.806us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	7.000s	406.806us	50	50	100.00
		aes_sideload	9.000s	406.743us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	116.470us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	116.470us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	116.470us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	116.470us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	116.470us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	7.000s	406.806us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	7.000s	406.806us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	287.501us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	287.501us	50	50	100.00
		aes_control_fi	45.000s	200.000ms	285	300	95.00
		aes_cipher_fi	31.000s	10.018ms	328	350	93.71
		aes_ctr_fi	6.000s	54.592us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	287.501us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	287.501us	50	50	100.00
		aes_control_fi	45.000s	200.000ms	285	300	95.00
		aes_cipher_fi	31.000s	10.018ms	328	350	93.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	31.000s	10.018ms	328	350	93.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	287.501us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	287.501us	50	50	100.00
		aes_control_fi	45.000s	200.000ms	285	300	95.00
		aes_ctr_fi	6.000s	54.592us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	287.501us	50	50	100.00
		aes_control_fi	45.000s	200.000ms	285	300	95.00
		aes_cipher_fi	31.000s	10.018ms	328	350	93.71
		aes_ctr_fi	6.000s	54.592us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	7.000s	443.491us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	287.501us	50	50	100.00
		aes_control_fi	45.000s	200.000ms	285	300	95.00
		aes_cipher_fi	31.000s	10.018ms	328	350	93.71
		aes_ctr_fi	6.000s	54.592us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	287.501us	50	50	100.00
		aes_control_fi	45.000s	200.000ms	285	300	95.00
		aes_cipher_fi	31.000s	10.018ms	328	350	93.71
		aes_ctr_fi	6.000s	54.592us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	287.501us	50	50	100.00
		aes_control_fi	45.000s	200.000ms	285	300	95.00
		aes_ctr_fi	6.000s	54.592us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	287.501us	50	50	100.00
		aes_control_fi	45.000s	200.000ms	285	300	95.00
		aes_cipher_fi	31.000s	10.018ms	328	350	93.71
V2S		TOTAL			942	985	95.63
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	17.000s	1.833ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1549	1602	96.69

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.27	97.66	94.71	98.80	93.40	97.99	91.11	98.85	97.59

Failure Buckets

Job timed out after * minutes has 17 failures:
- Test aes_cipher_fi has 12 failures.
  - 27.aes_cipher_fi.85471860106742599184165885390222849733380660114414956331368384048500610852861
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/27.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 40.aes_cipher_fi.62299834381886420797802986383370866253230168733244059558573174394169164781778
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/40.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 10 more failures.
- Test aes_control_fi has 5 failures.
  - 31.aes_control_fi.41903457181143918832068488999128580528550677473990404477685488696287123568404
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/31.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 68.aes_control_fi.19093475331474747854155222777160528678852626550683850330504238410165922766854
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/68.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 14.aes_cipher_fi.109866822160199215323069621286148798904099904126677796614901025735188473602368
    Line 145, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004976354 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004976354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 66.aes_cipher_fi.42426728074811074415143006193072287150431678205796044233453518174760697420826
    Line 130, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/66.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007700195 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007700195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 43.aes_control_fi.64234194034019443671181748770455706590678313149620416453682500608253400971350
    Line 144, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/43.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003595897 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003595897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 74.aes_control_fi.1974737378702930817236010119350853654411147314908023857630082672346354501301
    Line 149, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/74.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004297838 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004297838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

2.aes_stress_all_with_rand_reset.89768857163057971623278528601080688584285891283822424113582929616295186387861
Line 515, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 173985300 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 173985300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.43548742644973511520417360646141567090271612333221859533505196589418892789985
Line 1154, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 574006317 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 574006317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 4.aes_core_fi.111594045839279744192849198733735300607190720595453455215529489464377795856004
    Line 139, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006627296 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006627296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 18.aes_core_fi.61633477934014091118899999549857706082311054472679197956406026580532844388729
    Line 133, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/18.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005821413 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005821413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 4.aes_stress_all_with_rand_reset.19126132845217131050085196966730982158326926009773035689343551317268815522355
    Line 799, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1833449820 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1833449820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.aes_stress_all_with_rand_reset.42372011190349895039852492413652162819243885768267839072956648026905351019727
    Line 157, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  62643415 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  62643415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:929) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.67067069238564226302533476072788459005893395583665011593670758069734031270964
    Line 131, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 235839473 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 235839473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.110059342650223535279374708250260301834768135458823566980363590150393237311623
    Line 256, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 202589248 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 202589248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.77309235280881855636938192807648340478717698245228188068973783951769717761679
    Line 148, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 111260127 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 111260127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 14.aes_core_fi.52283471104074249122776545117749888495409596535444873278931750801422251624950
    Line 134, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/14.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10094798713 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10094798713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 35.aes_core_fi.17471262353006551758241916426950879314558807496407284613256250998088859572415
    Line 138, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/35.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10042684085 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x58943084, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10042684085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 55.aes_core_fi.109811334923669897081720048882535204131902398886956173581927087188542806543463
    Line 134, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/55.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011784427 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xf0a5a484, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10011784427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_control_fi has 1 failures.
  - 102.aes_control_fi.58918776369032200671003177733036744576811008144572965629003865535330301980787
    Line 147, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/102.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```