CSRNG Simulation Results

Friday May 02 2025 17:38:26 UTC

GitHub Revision: `c9ef9e5`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	13.000s	169.575us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	7.000s	227.845us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	59.410us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	21.000s	452.159us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	8.000s	80.173us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	8.000s	239.960us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	59.410us	20	20	100.00
		csrng_csr_aliasing	8.000s	80.173us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	25.000s	1.246ms	200	200	100.00
V2	alerts	csrng_alert	1.217m	6.043ms	500	500	100.00
V2	err	csrng_err	8.000s	69.585us	500	500	100.00
V2	cmds	csrng_cmds	6.133m	29.247ms	50	50	100.00
V2	life cycle	csrng_cmds	6.133m	29.247ms	50	50	100.00
V2	stress_all	csrng_stress_all	21.467m	104.466ms	50	50	100.00
V2	intr_test	csrng_intr_test	6.000s	110.968us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	20.524us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	13.000s	772.342us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	13.000s	772.342us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	7.000s	227.845us	5	5	100.00
		csrng_csr_rw	6.000s	59.410us	20	20	100.00
		csrng_csr_aliasing	8.000s	80.173us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	270.563us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	7.000s	227.845us	5	5	100.00
		csrng_csr_rw	6.000s	59.410us	20	20	100.00
		csrng_csr_aliasing	8.000s	80.173us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	270.563us	20	20	100.00
V2		TOTAL			1440	1440	100.00
V2S	tl_intg_err	csrng_sec_cm	9.000s	131.750us	5	5	100.00
		csrng_tl_intg_err	12.000s	555.230us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	9.000s	222.886us	50	50	100.00
		csrng_csr_rw	6.000s	59.410us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.217m	6.043ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	21.467m	104.466ms	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	25.000s	1.246ms	200	200	100.00
		csrng_err	8.000s	69.585us	500	500	100.00
		csrng_sec_cm	9.000s	131.750us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	25.000s	1.246ms	200	200	100.00
		csrng_err	8.000s	69.585us	500	500	100.00
		csrng_sec_cm	9.000s	131.750us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	25.000s	1.246ms	200	200	100.00
		csrng_err	8.000s	69.585us	500	500	100.00
		csrng_sec_cm	9.000s	131.750us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	25.000s	1.246ms	200	200	100.00
		csrng_err	8.000s	69.585us	500	500	100.00
		csrng_sec_cm	9.000s	131.750us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	25.000s	1.246ms	200	200	100.00
		csrng_err	8.000s	69.585us	500	500	100.00
		csrng_sec_cm	9.000s	131.750us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	25.000s	1.246ms	200	200	100.00
		csrng_err	8.000s	69.585us	500	500	100.00
		csrng_sec_cm	9.000s	131.750us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	25.000s	1.246ms	200	200	100.00
		csrng_err	8.000s	69.585us	500	500	100.00
		csrng_sec_cm	9.000s	131.750us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.217m	6.043ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	25.000s	1.246ms	200	200	100.00
		csrng_err	8.000s	69.585us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	21.467m	104.466ms	50	50	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.217m	6.043ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	12.000s	555.230us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	25.000s	1.246ms	200	200	100.00
		csrng_err	8.000s	69.585us	500	500	100.00
		csrng_sec_cm	9.000s	131.750us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	25.000s	1.246ms	200	200	100.00
		csrng_err	8.000s	69.585us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	25.000s	1.246ms	200	200	100.00
		csrng_err	8.000s	69.585us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	25.000s	1.246ms	200	200	100.00
		csrng_err	8.000s	69.585us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	25.000s	1.246ms	200	200	100.00
		csrng_err	8.000s	69.585us	500	500	100.00
		csrng_sec_cm	9.000s	131.750us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	25.000s	1.246ms	200	200	100.00
		csrng_err	8.000s	69.585us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.383m	3.306ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1620	1630	99.39

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.79	98.63	96.68	99.97	97.48	92.08	100.00	97.36	90.93

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test csrng_stress_all_with_rand_reset has 8 failures.
  - 0.csrng_stress_all_with_rand_reset.55146535116001765160798476555160096571572509460679037926007523790360085870932
    Line 105, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 717850319 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 717850319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.csrng_stress_all_with_rand_reset.72805403536607547558271301415633490296341306518186232542377779332559827743592
    Line 101, in log /nightly/runs/scratch/master/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1420811605 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1420811605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 2 failures:

Test csrng_stress_all_with_rand_reset has 2 failures.

1.csrng_stress_all_with_rand_reset.101448026119749985707939279712386437053030652593474467725120104372887164605681
Line 110, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  13471230 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @  13471230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.csrng_stress_all_with_rand_reset.16032779949604979110642942865754148864464165492954011987528253680850006421296
Line 104, in log /nightly/runs/scratch/master/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 167698180 ps: uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer.m_edn_push_seq[0] already started
  UVM_INFO @ 167698180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---