DMA Simulation Results

Friday May 02 2025 17:38:26 UTC

GitHub Revision: c9ef9e5

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	48.000s	622.740us	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	50.000s	2.056ms	25	25	100.00
V1	dma_generic_smoke	dma_generic_smoke	51.000s	385.391us	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	5.000s	32.560us	5	5	100.00
V1	csr_rw	dma_csr_rw	5.000s	58.515us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	16.000s	1.551ms	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	12.000s	441.153us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	5.000s	152.117us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	5.000s	58.515us	20	20	100.00
		dma_csr_aliasing	12.000s	441.153us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	2.517m	78.193ms	5	5	100.00
V2	dma_handshake_stress	dma_handshake_stress	18.550m	185.537ms	3	3	100.00
V2	dma_memory_stress	dma_memory_stress	31.350m	1.072s	3	3	100.00
V2	dma_generic_stress	dma_generic_stress	15.433m	302.302ms	4	5	80.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	18.550m	185.537ms	3	3	100.00
V2	dma_abort	dma_abort	1.150m	8.411ms	5	5	100.00
V2	dma_stress_all	dma_stress_all	7.350m	332.966ms	3	3	100.00
V2	intr_test	dma_intr_test	5.000s	15.072us	50	50	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	7.000s	157.766us	20	20	100.00
V2	tl_d_illegal_access	dma_tl_errors	7.000s	157.766us	20	20	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	5.000s	32.560us	5	5	100.00
		dma_csr_rw	5.000s	58.515us	20	20	100.00
		dma_csr_aliasing	12.000s	441.153us	5	5	100.00
		dma_same_csr_outstanding	6.000s	229.038us	20	20	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	5.000s	32.560us	5	5	100.00
		dma_csr_rw	5.000s	58.515us	20	20	100.00
		dma_csr_aliasing	12.000s	441.153us	5	5	100.00
		dma_same_csr_outstanding	6.000s	229.038us	20	20	100.00
V2		TOTAL			113	114	99.12
V2S	dma_illegal_addr_range	dma_mem_enabled	1.283m	973.075us	5	5	100.00
		dma_generic_stress	15.433m	302.302ms	4	5	80.00
		dma_handshake_stress	18.550m	185.537ms	3	3	100.00
V2S	tl_intg_err	dma_tl_intg_err	7.000s	1.865ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	dma_short_transfer	2.817m	106.070ms	5	5	100.00
		dma_longer_transfer	48.000s	263.913us	5	5	100.00
		TOTAL			303	304	99.67

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
75.62	96.97	95.19	96.93	96.02	82.72	82.76	97.77	41.10

Failure Buckets

• Job timed out after * minutes has 1 failures:
  • Test dma_generic_stress has 1 failures.

    • 4.dma_generic_stress.110801734300127379423144823697599511230514714950165332978059491332519501429296
      Log /nightly/runs/scratch/master/dma-sim-xcelium/4.dma_generic_stress/latest/run.log

        Job timed out after 60 minutes