EDN Simulation Results

Friday May 02 2025 17:38:26 UTC

GitHub Revision: c9ef9e5

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.660s 20.382us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 2.490s 24.926us 5 5 100.00
V1 csr_rw edn_csr_rw 2.620s 176.354us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.850s 261.925us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.870s 30.298us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 3.470s 29.733us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.620s 176.354us 20 20 100.00
edn_csr_aliasing 2.870s 30.298us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 7.580s 1.435ms 300 300 100.00
V2 csrng_commands edn_genbits 7.580s 1.435ms 300 300 100.00
V2 genbits edn_genbits 7.580s 1.435ms 300 300 100.00
V2 interrupts edn_intr 2.810s 22.577us 50 50 100.00
V2 alerts edn_alert 3.060s 50.969us 200 200 100.00
V2 errs edn_err 2.870s 20.741us 100 100 100.00
V2 disable edn_disable 2.520s 14.157us 50 50 100.00
edn_disable_auto_req_mode 3.000s 47.967us 50 50 100.00
V2 stress_all edn_stress_all 8.510s 382.205us 50 50 100.00
V2 intr_test edn_intr_test 2.600s 15.099us 50 50 100.00
V2 alert_test edn_alert_test 3.060s 51.161us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.730s 249.465us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.730s 249.465us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 2.490s 24.926us 5 5 100.00
edn_csr_rw 2.620s 176.354us 20 20 100.00
edn_csr_aliasing 2.870s 30.298us 5 5 100.00
edn_same_csr_outstanding 3.170s 75.334us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 2.490s 24.926us 5 5 100.00
edn_csr_rw 2.620s 176.354us 20 20 100.00
edn_csr_aliasing 2.870s 30.298us 5 5 100.00
edn_same_csr_outstanding 3.170s 75.334us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 10.120s 1.155ms 5 5 100.00
edn_tl_intg_err 5.360s 240.150us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 2.550s 18.761us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 3.060s 50.969us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 10.120s 1.155ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 10.120s 1.155ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 10.120s 1.155ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 10.120s 1.155ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 3.060s 50.969us 200 200 100.00
edn_sec_cm 10.120s 1.155ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 3.060s 50.969us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 5.360s 240.150us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 2.354m 6.523ms 32 50 64.00
V3 TOTAL 32 50 64.00
TOTAL 1112 1130 98.41

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.79 98.32 94.29 97.02 91.86 96.33 99.78 92.94

Failure Buckets