HMAC Simulation Results

Friday May 02 2025 17:38:26 UTC

GitHub Revision: c9ef9e5

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	14.470s	665.465us	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.580s	75.386us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.670s	56.466us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.210s	9.838ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.740s	2.475ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	13.203m	67.119ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.670s	56.466us	20	20	100.00
		hmac_csr_aliasing	8.740s	2.475ms	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.929m	17.670ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.404m	7.592ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.098m	6.821ms	30	30	100.00
		hmac_test_sha384_vectors	8.892m	14.257ms	75	75	100.00
		hmac_test_sha512_vectors	8.698m	11.833ms	75	75	100.00
		hmac_test_hmac256_vectors	15.950s	1.432ms	50	50	100.00
		hmac_test_hmac384_vectors	18.190s	753.000us	60	60	100.00
		hmac_test_hmac512_vectors	19.170s	5.884ms	75	75	100.00
V2	burst_wr	hmac_burst_wr	41.990s	8.344ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	19.646m	13.558ms	10	10	100.00
V2	error	hmac_error	1.467m	4.205ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.686m	8.660ms	10	10	100.00
V2	save_and_restore	hmac_smoke	14.470s	665.465us	10	10	100.00
		hmac_long_msg	1.929m	17.670ms	10	10	100.00
		hmac_back_pressure	1.404m	7.592ms	25	25	100.00
		hmac_datapath_stress	19.646m	13.558ms	10	10	100.00
		hmac_burst_wr	41.990s	8.344ms	50	50	100.00
		hmac_stress_all	29.473m	14.550ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	14.470s	665.465us	10	10	100.00
		hmac_long_msg	1.929m	17.670ms	10	10	100.00
		hmac_back_pressure	1.404m	7.592ms	25	25	100.00
		hmac_datapath_stress	19.646m	13.558ms	10	10	100.00
		hmac_wipe_secret	1.686m	8.660ms	10	10	100.00
		hmac_test_sha256_vectors	4.098m	6.821ms	30	30	100.00
		hmac_test_sha384_vectors	8.892m	14.257ms	75	75	100.00
		hmac_test_sha512_vectors	8.698m	11.833ms	75	75	100.00
		hmac_test_hmac256_vectors	15.950s	1.432ms	50	50	100.00
		hmac_test_hmac384_vectors	18.190s	753.000us	60	60	100.00
		hmac_test_hmac512_vectors	19.170s	5.884ms	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	14.470s	665.465us	10	10	100.00
		hmac_long_msg	1.929m	17.670ms	10	10	100.00
		hmac_back_pressure	1.404m	7.592ms	25	25	100.00
		hmac_datapath_stress	19.646m	13.558ms	10	10	100.00
		hmac_burst_wr	41.990s	8.344ms	50	50	100.00
		hmac_error	1.467m	4.205ms	10	10	100.00
		hmac_wipe_secret	1.686m	8.660ms	10	10	100.00
		hmac_test_sha256_vectors	4.098m	6.821ms	30	30	100.00
		hmac_test_sha384_vectors	8.892m	14.257ms	75	75	100.00
		hmac_test_sha512_vectors	8.698m	11.833ms	75	75	100.00
		hmac_test_hmac256_vectors	15.950s	1.432ms	50	50	100.00
		hmac_test_hmac384_vectors	18.190s	753.000us	60	60	100.00
		hmac_test_hmac512_vectors	19.170s	5.884ms	75	75	100.00
		hmac_stress_all	29.473m	14.550ms	50	50	100.00
V2	stress_all	hmac_stress_all	29.473m	14.550ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.170s	16.298us	50	50	100.00
V2	intr_test	hmac_intr_test	2.490s	27.545us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.200s	417.891us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.200s	417.891us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.580s	75.386us	5	5	100.00
		hmac_csr_rw	2.670s	56.466us	20	20	100.00
		hmac_csr_aliasing	8.740s	2.475ms	5	5	100.00
		hmac_same_csr_outstanding	3.400s	96.985us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.580s	75.386us	5	5	100.00
		hmac_csr_rw	2.670s	56.466us	20	20	100.00
		hmac_csr_aliasing	8.740s	2.475ms	5	5	100.00
		hmac_same_csr_outstanding	3.400s	96.985us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	2.390s	70.791us	5	5	100.00
		hmac_tl_intg_err	5.270s	240.779us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.270s	240.779us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	14.470s	665.465us	10	10	100.00
V3	stress_reset	hmac_stress_reset	6.720s	146.832us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	10.154m	34.295ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	2.190s	10.384us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.09	100.00	97.31	100.00	100.00	100.00	100.00	47.30