c9ef9e5| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.416m | 7.917ms | 50 | 50 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 40.530s | 5.736ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 2.200s | 23.516us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 2.170s | 36.821us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 4.950s | 118.419us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 2.660s | 42.923us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 2.280s | 24.825us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 2.170s | 36.821us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 2.660s | 42.923us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 155 | 155 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 15.090s | 439.162us | 50 | 50 | 100.00 |
| V2 | host_stress_all | i2c_host_stress_all | 54.412m | 82.001ms | 14 | 50 | 28.00 |
| V2 | host_maxperf | i2c_host_perf | 50.132m | 98.288ms | 50 | 50 | 100.00 |
| V2 | host_override | i2c_host_override | 2.190s | 30.665us | 50 | 50 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 4.577m | 18.762ms | 50 | 50 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 2.560m | 14.424ms | 50 | 50 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 2.930s | 120.288us | 50 | 50 | 100.00 |
| i2c_host_fifo_fmt_empty | 26.690s | 536.787us | 50 | 50 | 100.00 | ||
| i2c_host_fifo_reset_rx | 12.750s | 851.586us | 50 | 50 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 3.924m | 18.806ms | 50 | 50 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 43.060s | 1.821ms | 50 | 50 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 6.910s | 186.215us | 15 | 50 | 30.00 |
| V2 | target_glitch | i2c_target_glitch | 12.030s | 2.508ms | 2 | 2 | 100.00 |
| V2 | target_stress_all | i2c_target_stress_all | 33.509m | 89.325ms | 49 | 50 | 98.00 |
| V2 | target_maxperf | i2c_target_perf | 8.760s | 3.076ms | 50 | 50 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 1.111m | 12.340ms | 50 | 50 | 100.00 |
| i2c_target_intr_smoke | 11.190s | 1.435ms | 50 | 50 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 3.530s | 291.144us | 50 | 50 | 100.00 |
| i2c_target_fifo_reset_tx | 3.250s | 677.876us | 50 | 50 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 22.466m | 68.220ms | 50 | 50 | 100.00 |
| i2c_target_stress_rd | 1.111m | 12.340ms | 50 | 50 | 100.00 | ||
| i2c_target_intr_stress_wr | 5.269m | 23.775ms | 50 | 50 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 11.170s | 6.082ms | 50 | 50 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 1.139m | 3.608ms | 43 | 50 | 86.00 |
| V2 | bad_address | i2c_target_bad_addr | 9.440s | 9.810ms | 50 | 50 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 38.100s | 10.145ms | 20 | 50 | 40.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 5.010s | 515.861us | 50 | 50 | 100.00 |
| i2c_target_fifo_watermarks_tx | 3.240s | 178.977us | 48 | 50 | 96.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 50.132m | 98.288ms | 50 | 50 | 100.00 |
| i2c_host_perf_precise | 16.405m | 23.200ms | 50 | 50 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 43.060s | 1.821ms | 50 | 50 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 34.050s | 2.224ms | 50 | 50 | 100.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 5.140s | 520.258us | 50 | 50 | 100.00 |
| i2c_target_nack_acqfull_addr | 5.180s | 544.672us | 50 | 50 | 100.00 | ||
| i2c_target_nack_txstretch | 3.420s | 3.306ms | 34 | 50 | 68.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 25.970s | 3.485ms | 50 | 50 | 100.00 |
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 4.460s | 2.145ms | 50 | 50 | 100.00 |
| V2 | alert_test | i2c_alert_test | 2.120s | 16.865us | 50 | 50 | 100.00 |
| V2 | intr_test | i2c_intr_test | 2.160s | 45.958us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 3.650s | 600.551us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 3.650s | 600.551us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 2.200s | 23.516us | 5 | 5 | 100.00 |
| i2c_csr_rw | 2.170s | 36.821us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.660s | 42.923us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 2.400s | 111.455us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 2.200s | 23.516us | 5 | 5 | 100.00 |
| i2c_csr_rw | 2.170s | 36.821us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 2.660s | 42.923us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 2.400s | 111.455us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1665 | 1792 | 92.91 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 3.740s | 181.328us | 20 | 20 | 100.00 |
| i2c_sec_cm | 2.420s | 675.248us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 3.740s | 181.328us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 41.370s | 845.427us | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 4.160s | 286.897us | 0 | 50 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 54.490s | 16.520ms | 0 | 10 | 0.00 |
| V3 | TOTAL | 0 | 70 | 0.00 | |||
| TOTAL | 1845 | 2042 | 90.35 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 87.97 | 97.25 | 89.70 | 74.17 | 72.02 | 94.18 | 98.52 | 89.96 |
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 44 failures:
0.i2c_host_stress_all.77064716676163507183604096125976822527453000335268554230446043693066784040071
Line 133, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 269341625576 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @3465506
3.i2c_host_stress_all.38073328924114722435883999271538172808831034232745846812128005379255642715716
Line 167, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 8083165001 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @1510026
... and 28 more failures.
0.i2c_host_mode_toggle.21835538513876117996760474570636860126255845865359691139169238955612546839696
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 186215404 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @117069
3.i2c_host_mode_toggle.51763451876356293310187859319134240811945323948879659279502074160598307623416
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 574535052 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @34039
... and 12 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 34 failures:
1.i2c_target_unexp_stop.69360316830021140339591041665309026350080826219406416193031816526864669365828
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 64470990 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 84 [0x54])
UVM_INFO @ 64470990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_unexp_stop.13361099939228736643990179254789309099257483299912315777424042381341663291728
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 76191523 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 121 [0x79])
UVM_INFO @ 76191523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 32 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 30 failures:
0.i2c_target_hrst.27508808169827740803115847524347054608497529870574161253370369247637354044803
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10307050228 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10307050228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_hrst.106558806419783410551206427821828838142402187200911927411342782607680885612899
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10109520070 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10109520070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 28 more failures.
UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
0.i2c_host_stress_all_with_rand_reset.42954451110249611119041644337549918235299736769878575105936684526715066536944
Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 110460846 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 110460846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.67075455718005976905140526701558231509681978037447890691263328863748137627429
Line 110, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 845427226 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 845427226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
1.i2c_target_stress_all_with_rand_reset.107176540064363451646110884098765116870331751009672100667530904503575473540537
Line 108, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1664248134 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1664248134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_target_stress_all_with_rand_reset.34612463450983601383231208296421232356120091282073106527069333144897081677006
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 768971259 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 768971259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 16 failures:
0.i2c_target_nack_txstretch.83527308052505514709934187921399370098494053924441312317216933373416677057161
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 570797654 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 570797654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_nack_txstretch.111335307960964526002121501099141280064973239303769791468181332121705931669798
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 140372227 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 140372227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 14 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 14 failures:
4.i2c_host_mode_toggle.69048359354515974682336848620228656732629398680553028947875695772578155924542
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 126854496 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
5.i2c_host_mode_toggle.29202555828702210866215988362591899335422463896162215506573589312375818756157
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 78189960 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 12 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 11 failures:
0.i2c_target_unexp_stop.10691123219360209722751716926213738832905427653904388465653966569010741974060
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 123390015 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 123390015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.i2c_target_unexp_stop.57177293925012393445870655582029820412878308226144281822481357290784926240811
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/9.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 142007021 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 142007021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 7 failures:
13.i2c_target_stretch.16888580722282396388973153700525321233165452134059666035132005566479966939123
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/13.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10001149200 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10001149200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.i2c_target_stretch.99502644031056146703924620538545539016782448209101179941593289208355668939699
Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/25.i2c_target_stretch/latest/run.log
UVM_FATAL @ 10011328126 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
UVM_INFO @ 10011328126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 5 failures:
7.i2c_target_unexp_stop.94486357718548612310489777454791615065600599604215095472999347447477046879048
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 151643941 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 151643941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.i2c_target_unexp_stop.87514468200334209249840644259612603469912411009509988728844430472930617309475
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 591392246 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 591392246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 4 failures:
15.i2c_host_mode_toggle.46561324816651465018503848702088436385428769017225871788555727575094380176959
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/15.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 105814184 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x4e716d14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 105814184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.i2c_host_mode_toggle.45195091113158544840103920343019174043792514350250046514296684404614832561218
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/19.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 283914385 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x9f344794, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 283914385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Job timed out after * minutes has 4 failures:
23.i2c_host_stress_all.96642961337511783651941344716979728508129274999572510066572571795656446638199
Log /nightly/runs/scratch/master/i2c-sim-vcs/23.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
30.i2c_host_stress_all.105153774372689046129998883078229582875539424735177922645612384469249842642757
Log /nightly/runs/scratch/master/i2c-sim-vcs/30.i2c_host_stress_all/latest/run.log
Job timed out after 60 minutes
... and 2 more failures.
Error-[NOA] Null object access has 3 failures:
16.i2c_host_mode_toggle.26289492154864251964212372585862291954977719126391728043187332101209604330217
Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/16.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
17.i2c_host_mode_toggle.88379176555598253837508721816818734792704741996396479977989496677159308551211
Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/17.i2c_host_mode_toggle/latest/run.log
Error-[NOA] Null object access
../src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
The object at dereference depth 0 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:832) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
0.i2c_target_stress_all_with_rand_reset.29641498023783667340254870728499878895193200645064153767454676120358342936906
Line 145, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16520406725 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 16520406725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_stress_all_with_rand_reset.48677606639884410404193702565516759337234562897672925988011134062126107122725
Line 112, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 974550385 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 974550385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
11.i2c_target_fifo_watermarks_tx.70670805357570415961875682020815529476517821219530266043650976008753685189452
Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/11.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
49.i2c_target_fifo_watermarks_tx.105865160684838656179023031788895306232151191727118072558914054748555939950597
Line 115, in log /nightly/runs/scratch/master/i2c-sim-vcs/49.i2c_target_fifo_watermarks_tx/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 2 failures:
18.i2c_host_stress_all.82619160409702844864683522599979877921344726279419801540017091726171525178179
Line 269, in log /nightly/runs/scratch/master/i2c-sim-vcs/18.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 65094318254 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @20979044
20.i2c_host_stress_all.96144414513940122975695451784336516194680057957599853345373398726581057513293
Line 206, in log /nightly/runs/scratch/master/i2c-sim-vcs/20.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 46258350594 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @1255602
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
22.i2c_target_stress_all.93141447385481326754394939337180151013007558397540958909152946199854370028471
Line 108, in log /nightly/runs/scratch/master/i2c-sim-vcs/22.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 153022137927 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 153022137927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---