KEYMGR Simulation Results

Friday May 02 2025 17:38:26 UTC

GitHub Revision: `c9ef9e5`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	32.530s	3.209ms	50	50	100.00
V1	random	keymgr_random	49.840s	3.690ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.490s	21.097us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.540s	49.075us	15	20	75.00
V1	csr_bit_bash	keymgr_csr_bit_bash	19.610s	2.755ms	2	5	40.00
V1	csr_aliasing	keymgr_csr_aliasing	9.050s	1.802ms	3	5	60.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.140s	123.156us	16	20	80.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.540s	49.075us	15	20	75.00
		keymgr_csr_aliasing	9.050s	1.802ms	3	5	60.00
V1		TOTAL			141	155	90.97
V2	cfgen_during_op	keymgr_cfg_regwen	1.196m	3.693ms	50	50	100.00
V2	sideload	keymgr_sideload	46.020s	2.015ms	50	50	100.00
		keymgr_sideload_kmac	43.710s	1.718ms	50	50	100.00
		keymgr_sideload_aes	31.440s	1.402ms	50	50	100.00
		keymgr_sideload_otbn	40.870s	1.783ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	17.670s	880.380us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	13.210s	346.681us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	11.970s	904.172us	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	36.650s	1.787ms	49	50	98.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	49.760s	2.607ms	49	50	98.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	20.180s	2.946ms	49	50	98.00
V2	stress_all	keymgr_stress_all	4.450m	14.154ms	50	50	100.00
V2	intr_test	keymgr_intr_test	2.190s	20.460us	50	50	100.00
V2	alert_test	keymgr_alert_test	2.800s	30.889us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.420s	373.894us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.420s	373.894us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.490s	21.097us	5	5	100.00
		keymgr_csr_rw	2.540s	49.075us	15	20	75.00
		keymgr_csr_aliasing	9.050s	1.802ms	3	5	60.00
		keymgr_same_csr_outstanding	4.060s	99.072us	14	20	70.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.490s	21.097us	5	5	100.00
		keymgr_csr_rw	2.540s	49.075us	15	20	75.00
		keymgr_csr_aliasing	9.050s	1.802ms	3	5	60.00
		keymgr_same_csr_outstanding	4.060s	99.072us	14	20	70.00
V2		TOTAL			729	740	98.51
V2S	sec_cm_additional_check	keymgr_sec_cm	17.420s	2.323ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	17.420s	2.323ms	5	5	100.00
		keymgr_tl_intg_err	7.000s	810.522us	12	20	60.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.750s	356.999us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.750s	356.999us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.750s	356.999us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.750s	356.999us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	10.110s	298.986us	10	20	50.00
V2S	prim_count_check	keymgr_sec_cm	17.420s	2.323ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	17.420s	2.323ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.000s	810.522us	12	20	60.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.750s	356.999us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.196m	3.693ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	49.840s	3.690ms	50	50	100.00
		keymgr_csr_rw	2.540s	49.075us	15	20	75.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	49.840s	3.690ms	50	50	100.00
		keymgr_csr_rw	2.540s	49.075us	15	20	75.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	49.840s	3.690ms	50	50	100.00
		keymgr_csr_rw	2.540s	49.075us	15	20	75.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	13.210s	346.681us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	49.760s	2.607ms	49	50	98.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	49.760s	2.607ms	49	50	98.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	49.840s	3.690ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	23.880s	3.202ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	17.420s	2.323ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	17.420s	2.323ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	17.420s	2.323ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	33.210s	3.053ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	13.210s	346.681us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	17.420s	2.323ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	17.420s	2.323ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	17.420s	2.323ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	33.210s	3.053ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	33.210s	3.053ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	17.420s	2.323ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	33.210s	3.053ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	17.420s	2.323ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	33.210s	3.053ms	50	50	100.00
V2S		TOTAL			147	165	89.09
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	25.030s	736.069us	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			1046	1110	94.23

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.42	99.06	98.07	98.35	97.67	98.92	98.63	91.21

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 38 failures:

Test keymgr_shadow_reg_errors_with_csr_rw has 10 failures.

0.keymgr_shadow_reg_errors_with_csr_rw.98760918033765786851635000768394690790602871626222503903972129189746430567580
Line 82, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
  UVM_ERROR @  26399234 ps: (keymgr_csr_assert_fpv.sv:466) [ASSERT FAILED] attest_sw_binding_7_rd_A
  UVM_INFO @  26399234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.keymgr_shadow_reg_errors_with_csr_rw.10255766746810727367994831824566721650187835769252140381518040052013728176132
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[20] & 'hffffffff)))'
  UVM_ERROR @  66560747 ps: (keymgr_csr_assert_fpv.sv:466) [ASSERT FAILED] attest_sw_binding_7_rd_A
  UVM_INFO @  66560747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test keymgr_same_csr_outstanding has 6 failures.

0.keymgr_same_csr_outstanding.24461888354521330595129769010352411501230436293116489691436361761804885241464
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
  UVM_ERROR @ 117447883 ps: (keymgr_csr_assert_fpv.sv:451) [ASSERT FAILED] attest_sw_binding_4_rd_A
  UVM_INFO @ 117447883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.keymgr_same_csr_outstanding.25182078012544112903484601145442389196914298640814872467985473734597761161881
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
  UVM_ERROR @  61303361 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_2_rd_A
  UVM_INFO @  61303361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test keymgr_csr_rw has 5 failures.

1.keymgr_csr_rw.79323812457571383678549692966872063653287707604990524961464621848473074846854
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[13] & 'hffffffff)))'
  UVM_ERROR @   9222996 ps: (keymgr_csr_assert_fpv.sv:431) [ASSERT FAILED] attest_sw_binding_0_rd_A
  UVM_INFO @   9222996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.keymgr_csr_rw.82418731967087794608871418745596223622689154748704302287145135264034649797479
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/6.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
  UVM_ERROR @  16232554 ps: (keymgr_csr_assert_fpv.sv:456) [ASSERT FAILED] attest_sw_binding_5_rd_A
  UVM_INFO @  16232554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test keymgr_csr_bit_bash has 3 failures.

1.keymgr_csr_bit_bash.82044409972325343873005560092571757628468512095141101038008189494247351434966
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
  UVM_ERROR @ 478685424 ps: (keymgr_csr_assert_fpv.sv:446) [ASSERT FAILED] attest_sw_binding_3_rd_A
  UVM_INFO @ 478685424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.keymgr_csr_bit_bash.76726509139596328653477142134543266250906742381140195640188961922081045782892
Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[13] & 'hffffffff)))'
  UVM_ERROR @ 1476693258 ps: (keymgr_csr_assert_fpv.sv:431) [ASSERT FAILED] attest_sw_binding_0_rd_A
  UVM_INFO @ 1476693258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test keymgr_csr_aliasing has 2 failures.

2.keymgr_csr_aliasing.40128844187978222975644469531648997605524118785699523089973403693652528733437
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
  UVM_ERROR @ 978044046 ps: (keymgr_csr_assert_fpv.sv:426) [ASSERT FAILED] sealing_sw_binding_7_rd_A
  UVM_INFO @ 978044046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.keymgr_csr_aliasing.43150998315938479387281944633940648337847801750543998635915241277679145248629
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_csr_aliasing/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
  UVM_ERROR @ 1190198489 ps: (keymgr_csr_assert_fpv.sv:461) [ASSERT FAILED] attest_sw_binding_6_rd_A
  UVM_INFO @ 1190198489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more tests.

UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test keymgr_stress_all_with_rand_reset has 19 failures.
  - 1.keymgr_stress_all_with_rand_reset.16457412012114979428561367307655664612942737283326849400247820288743449550909
    Line 665, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1082178101 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1082178101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.keymgr_stress_all_with_rand_reset.74851413445434557982046443485595300359408504646905593771875104683884016308106
    Line 357, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 338045579 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 338045579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.
UVM_ERROR (cip_base_scoreboard.sv:349) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
- Test keymgr_kmac_rsp_err has 1 failures.
  - 10.keymgr_kmac_rsp_err.54851404029099022081818279080054205780797985424837778647201655223512035672390
    Line 531, in log /nightly/runs/scratch/master/keymgr-sim-vcs/10.keymgr_kmac_rsp_err/latest/run.log
```
  UVM_ERROR @ 126416803 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 126416803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sw_invalid_input has 1 failures.
  - 16.keymgr_sw_invalid_input.49167398887038079151792413325757678980374784110233311916960857237455366860876
    Line 313, in log /nightly/runs/scratch/master/keymgr-sim-vcs/16.keymgr_sw_invalid_input/latest/run.log
```
  UVM_ERROR @  43289249 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  43289249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:263) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_hwsw_invalid_input has 1 failures.
  - 7.keymgr_hwsw_invalid_input.9596095743921062307456804044775625391847868611440555304261520529714912228831
    Line 379, in log /nightly/runs/scratch/master/keymgr-sim-vcs/7.keymgr_hwsw_invalid_input/latest/run.log
```
  UVM_ERROR @  75189959 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  75189959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 15.keymgr_stress_all_with_rand_reset.92064071705949778964817895434528404602932920332545199275031241828775247907415
    Line 130, in log /nightly/runs/scratch/master/keymgr-sim-vcs/15.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  83141413 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_4
  UVM_INFO @  83141413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:689) [scoreboard] Check failed edn_fifos[*].used() == * (* [*] vs * [*]) has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 35.keymgr_lc_disable.72645571992679328153921138105941469041894375323503220776755246864090913884097
    Line 137, in log /nightly/runs/scratch/master/keymgr-sim-vcs/35.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  25725575 ps: (keymgr_scoreboard.sv:689) [uvm_test_top.env.scoreboard] Check failed edn_fifos[0].used() == 2 (0 [0x0] vs 2 [0x2])
  UVM_INFO @  25725575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_sync_async_fault_cross_vseq.sv:38) [keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] || act_fault_status[keymgr_pkg::FaultKmacOut] == * (* [*] vs * [*]) has 1 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 46.keymgr_sync_async_fault_cross.45229691996246797879594376298285276872541396770267926006706744023743667663016
    Line 168, in log /nightly/runs/scratch/master/keymgr-sim-vcs/46.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @ 292738310 ps: (keymgr_sync_async_fault_cross_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] ||                 act_fault_status[keymgr_pkg::FaultKmacOut] == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 292738310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:832) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 47.keymgr_stress_all_with_rand_reset.40407468424018684398548086262330091848394400511724880930922796408877740265459
    Line 1213, in log /nightly/runs/scratch/master/keymgr-sim-vcs/47.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1679035763 ps: (cip_base_vseq.sv:832) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1679035763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```