KMAC/MASKED Simulation Results

Friday May 02 2025 17:38:26 UTC

GitHub Revision: `c9ef9e5`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.670m	21.631ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.610s	30.629us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.500s	107.446us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.130s	298.313us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.390s	522.089us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	4.150s	815.465us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.500s	107.446us	20	20	100.00
		kmac_csr_aliasing	11.390s	522.089us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.160s	58.354us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.930s	41.428us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.021h	1.466s	50	50	100.00
V2	burst_write	kmac_burst_write	22.699m	30.892ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.561m	18.684ms	5	5	100.00
		kmac_test_vectors_sha3_256	31.402m	238.333ms	5	5	100.00
		kmac_test_vectors_sha3_384	27.576m	376.110ms	5	5	100.00
		kmac_test_vectors_sha3_512	18.676m	130.602ms	5	5	100.00
		kmac_test_vectors_shake_128	4.177m	90.447ms	5	5	100.00
		kmac_test_vectors_shake_256	39.765m	950.669ms	5	5	100.00
		kmac_test_vectors_kmac	4.770s	103.570us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.020s	62.513us	5	5	100.00
V2	sideload	kmac_sideload	7.749m	33.025ms	50	50	100.00
V2	app	kmac_app	6.286m	14.252ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.801m	8.685ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.910m	13.195ms	50	50	100.00
V2	error	kmac_error	7.772m	15.348ms	50	50	100.00
V2	key_error	kmac_key_error	19.130s	5.902ms	49	50	98.00
V2	sideload_invalid	kmac_sideload_invalid	11.780s	1.183ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	44.540s	2.189ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	47.420s	7.519ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.336m	28.692ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	51.630s	13.351ms	50	50	100.00
V2	stress_all	kmac_stress_all	44.154m	38.963ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.340s	26.954us	50	50	100.00
V2	alert_test	kmac_alert_test	2.340s	70.236us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	5.160s	624.363us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	5.160s	624.363us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.610s	30.629us	5	5	100.00
		kmac_csr_rw	2.500s	107.446us	20	20	100.00
		kmac_csr_aliasing	11.390s	522.089us	5	5	100.00
		kmac_same_csr_outstanding	4.290s	127.184us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.610s	30.629us	5	5	100.00
		kmac_csr_rw	2.500s	107.446us	20	20	100.00
		kmac_csr_aliasing	11.390s	522.089us	5	5	100.00
		kmac_same_csr_outstanding	4.290s	127.184us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.450s	113.695us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.450s	113.695us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.450s	113.695us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.450s	113.695us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.580s	349.916us	14	20	70.00
V2S	tl_intg_err	kmac_sec_cm	1.267m	27.445ms	5	5	100.00
		kmac_tl_intg_err	6.480s	809.193us	16	20	80.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.480s	809.193us	16	20	80.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	51.630s	13.351ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.670m	21.631ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.749m	33.025ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.450s	113.695us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.267m	27.445ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.267m	27.445ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.267m	27.445ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.670m	21.631ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	51.630s	13.351ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.267m	27.445ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.139m	33.152ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.670m	21.631ms	50	50	100.00
V2S		TOTAL			65	75	86.67
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.279m	2.610ms	3	10	30.00
V3		TOTAL			3	10	30.00
		TOTAL			922	940	98.09

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.42	99.03	94.47	99.89	80.28	97.03	99.37	97.86

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 9 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 5 failures.

1.kmac_shadow_reg_errors_with_csr_rw.52925980884646869758980809907910998246449403933063911243579328150678252298138
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
  UVM_ERROR @ 265763260 ps: (kmac_csr_assert_fpv.sv:502) [ASSERT FAILED] prefix_2_rd_A
  UVM_INFO @ 265763260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.kmac_shadow_reg_errors_with_csr_rw.58278161507990392841272286563083997343236989467391991763552557465690721158654
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
  UVM_ERROR @ 114458750 ps: (kmac_csr_assert_fpv.sv:537) [ASSERT FAILED] prefix_9_rd_A
  UVM_INFO @ 114458750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test kmac_tl_intg_err has 4 failures.

1.kmac_tl_intg_err.53028488117175594010570340289449254844987391298240875869618527586213583994643
Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
  UVM_ERROR @  42052874 ps: (kmac_csr_assert_fpv.sv:537) [ASSERT FAILED] prefix_9_rd_A
  UVM_INFO @  42052874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.kmac_tl_intg_err.93537980940852667158527470559071372117364498648645996180396774793965589162451
Line 79, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/14.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
  UVM_ERROR @   9994243 ps: (kmac_csr_assert_fpv.sv:532) [ASSERT FAILED] prefix_8_rd_A
  UVM_INFO @   9994243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 0.kmac_stress_all_with_rand_reset.67450462853936319828067735558517062619480066231039802678021390455461594762463
    Line 130, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7735451982 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 7735451982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.kmac_stress_all_with_rand_reset.61115336455172234658317297997898804404010054834096651067481860498061003878078
    Line 119, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1004938920 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1004938920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 2.kmac_shadow_reg_errors_with_csr_rw.15458792859187598806900837026536798068042895165143812059398104204699346801218
    Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @   8549736 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1060797315 [0x3f3a7b83] vs 2843837855 [0xa981859f]) Regname: kmac_reg_block.prefix_5 reset value: 0x0
  UVM_INFO @   8549736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 8.kmac_stress_all_with_rand_reset.75343908254913588720515811050706687088286928195705316416399462136721828424455
    Line 116, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13313915733 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 13313915733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 39.kmac_key_error.102645332269038693913480110085222254902509808152025993924474294481341056687590
    Line 94, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/39.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 3223275359 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 3223275359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```