KMAC/UNMASKED Simulation Results

Friday May 02 2025 17:38:26 UTC

GitHub Revision: `c9ef9e5`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.264m	39.881ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.490s	201.288us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.710s	94.891us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.610s	5.377ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.600s	1.582ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.830s	178.321us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.710s	94.891us	20	20	100.00
		kmac_csr_aliasing	10.600s	1.582ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.260s	17.562us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	3.260s	541.125us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	39.873m	223.341ms	50	50	100.00
V2	burst_write	kmac_burst_write	16.177m	151.399ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.760m	334.297ms	5	5	100.00
		kmac_test_vectors_sha3_256	22.288m	58.378ms	5	5	100.00
		kmac_test_vectors_sha3_384	18.358m	58.805ms	5	5	100.00
		kmac_test_vectors_sha3_512	14.601m	32.761ms	5	5	100.00
		kmac_test_vectors_shake_128	40.783m	360.103ms	5	5	100.00
		kmac_test_vectors_shake_256	25.705m	89.289ms	5	5	100.00
		kmac_test_vectors_kmac	4.200s	409.941us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.600s	64.455us	5	5	100.00
V2	sideload	kmac_sideload	7.349m	21.688ms	50	50	100.00
V2	app	kmac_app	4.580m	31.972ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.701m	48.827ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.102m	39.402ms	50	50	100.00
V2	error	kmac_error	6.389m	39.793ms	50	50	100.00
V2	key_error	kmac_key_error	14.530s	10.117ms	49	50	98.00
V2	sideload_invalid	kmac_sideload_invalid	2.252m	10.017ms	32	50	64.00
V2	edn_timeout_error	kmac_edn_timeout_error	40.990s	6.971ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	36.960s	1.469ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.028m	69.228ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	25.750s	2.461ms	50	50	100.00
V2	stress_all	kmac_stress_all	31.463m	1.429s	50	50	100.00
V2	intr_test	kmac_intr_test	2.370s	31.438us	50	50	100.00
V2	alert_test	kmac_alert_test	2.300s	74.707us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.980s	2.945ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.980s	2.945ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.490s	201.288us	5	5	100.00
		kmac_csr_rw	2.710s	94.891us	20	20	100.00
		kmac_csr_aliasing	10.600s	1.582ms	5	5	100.00
		kmac_same_csr_outstanding	4.390s	1.857ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.490s	201.288us	5	5	100.00
		kmac_csr_rw	2.710s	94.891us	20	20	100.00
		kmac_csr_aliasing	10.600s	1.582ms	5	5	100.00
		kmac_same_csr_outstanding	4.390s	1.857ms	20	20	100.00
V2		TOTAL			721	740	97.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.230s	442.072us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.230s	442.072us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.230s	442.072us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.230s	442.072us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	6.230s	364.426us	13	20	65.00
V2S	tl_intg_err	kmac_sec_cm	1.065m	10.527ms	5	5	100.00
		kmac_tl_intg_err	6.630s	784.440us	11	20	55.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.630s	784.440us	11	20	55.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	25.750s	2.461ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.264m	39.881ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.349m	21.688ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.230s	442.072us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.065m	10.527ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.065m	10.527ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.065m	10.527ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.264m	39.881ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	25.750s	2.461ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.065m	10.527ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.661m	62.636ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.264m	39.881ms	50	50	100.00
V2S		TOTAL			59	75	78.67
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.024m	2.820ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			900	940	95.74

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.68	97.17	94.38	100.00	72.73	95.98	99.35	96.13

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 16 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 7 failures.

1.kmac_shadow_reg_errors_with_csr_rw.74237819222257357421893724081900519710363176839820167367044410403026314744092
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
  UVM_ERROR @  67669120 ps: (kmac_csr_assert_fpv.sv:487) [ASSERT FAILED] entropy_period_rd_A
  UVM_INFO @  67669120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.kmac_shadow_reg_errors_with_csr_rw.22715181354368580697240289300761161976622765528735643252795878697191528632685
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
  UVM_ERROR @  69890303 ps: (kmac_csr_assert_fpv.sv:512) [ASSERT FAILED] prefix_4_rd_A
  UVM_INFO @  69890303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test kmac_tl_intg_err has 9 failures.

4.kmac_tl_intg_err.30343813421935774075741783138676078440439350587258864201355343973102598853815
Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[46] & 'hffffffff)))'
  UVM_ERROR @  38786722 ps: (kmac_csr_assert_fpv.sv:527) [ASSERT FAILED] prefix_7_rd_A
  UVM_INFO @  38786722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.kmac_tl_intg_err.57024430174057390064733677719438597837541109490314465605908706772273861541843
Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
  UVM_ERROR @  15469837 ps: (kmac_csr_assert_fpv.sv:522) [ASSERT FAILED] prefix_6_rd_A
  UVM_INFO @  15469837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 0.kmac_stress_all_with_rand_reset.24537359425266929474828572533492087252751467560142329418929476694655644465607
    Line 109, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1804106716 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1804106716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.kmac_stress_all_with_rand_reset.6071190625844590516595604197065461025364436658908182442811547898456365454001
    Line 167, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1675006574 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1675006574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 3 failures:
- Test kmac_sideload_invalid has 3 failures.
  - 3.kmac_sideload_invalid.97067977760988836519494733179547945934965142741396840734255803489092054496327
    Line 88, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10712600042 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xb5178000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
  UVM_INFO @ 10712600042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.kmac_sideload_invalid.102210515114560074841901775033139127221419898035337244802120241255843051533868
    Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/9.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10288253042 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf9dc9000, Comparison=CompareOpEq, exp_data=0x1, call_count=15)
  UVM_INFO @ 10288253042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 0.kmac_sideload_invalid.110650168493193012400668725044482825709523885011840318293141709796817764313106
    Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10065815468 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x110ae000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
  UVM_INFO @ 10065815468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 48.kmac_sideload_invalid.75508056086266830832487604435627665067766772570936278484953762148257631610146
    Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/48.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10038949006 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x5d2d8000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
  UVM_INFO @ 10038949006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 1.kmac_sideload_invalid.83268641053606774489114178801961850207559023000186315396056235633136667368806
    Line 83, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10092101713 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9be2d000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
  UVM_INFO @ 10092101713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 17.kmac_sideload_invalid.59401692581772407942656498533139633422908610263850295347484381979851975773060
    Line 84, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/17.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10059565950 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x49372000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
  UVM_INFO @ 10059565950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 7.kmac_stress_all_with_rand_reset.4717772906767029615179275243868369627109898061759616754896685282160249210530
    Line 94, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6847324115 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6847324115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.kmac_stress_all_with_rand_reset.54992507041474213939703863391756918102921198104218779085955247049699518910749
    Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6812423055 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6812423055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 12.kmac_sideload_invalid.56367567544492541584709755399327960406039001898330284745757738098714779743385
    Line 77, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/12.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10046288310 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x8b9d8000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
  UVM_INFO @ 10046288310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 19.kmac_sideload_invalid.64606801050204488178543567894990946414556945309539337131736252772933199784949
    Line 77, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/19.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10128370600 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7af2c000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
  UVM_INFO @ 10128370600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 31.kmac_sideload_invalid.55190068341183066212410787263135352544676052297156074924990305101757055036181
    Line 83, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/31.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10584169302 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x71752000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
  UVM_INFO @ 10584169302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 38.kmac_sideload_invalid.73636900290739981132876708740031942800107371131681512131134858131239449317505
    Line 83, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/38.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10263052137 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xdfe77000, Comparison=CompareOpEq, exp_data=0x1, call_count=10)
  UVM_INFO @ 10263052137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 2.kmac_sideload_invalid.111128946513903308636561174106916553329230088400107858953362410988641789139318
    Line 77, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10573630909 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x96efa000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
  UVM_INFO @ 10573630909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 6.kmac_sideload_invalid.31883790994637438711250498870371323863452834564094465767066987278999469881314
    Line 90, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/6.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10988337185 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x16b42000, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
  UVM_INFO @ 10988337185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 7.kmac_sideload_invalid.93035241643698741510819985715963620424915894097720329801287377931572266102202
    Line 74, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/7.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10016891665 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x43447000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 10016891665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 16.kmac_key_error.3773258980329218635683545295275701109938105894803705501033211193308000011641
    Line 98, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/16.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 2317008253 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 2317008253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 21.kmac_sideload_invalid.34277375626520494313866987282221674941485512577463026968555622484013623122284
    Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/21.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10141073298 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x708d6000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
  UVM_INFO @ 10141073298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 26.kmac_sideload_invalid.89641751915715468298249474557295841439022371872714780267912640846548417569306
    Line 83, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/26.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10058251408 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x81960000, Comparison=CompareOpEq, exp_data=0x1, call_count=9)
  UVM_INFO @ 10058251408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 45.kmac_sideload_invalid.99884522070534706913949038982038863394559748444220976745448230748576365925658
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/45.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10016410588 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x25f42000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10016410588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 49.kmac_sideload_invalid.102553831353414657475104846141417756974826984023109355418971910696199101300691
    Line 85, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/49.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10457816991 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbd5d5000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
  UVM_INFO @ 10457816991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```