MBX Simulation Results

Friday May 02 2025 17:38:26 UTC

GitHub Revision: c9ef9e5

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 mbx_smoke mbx_smoke 1.683m 8.438ms 2 2 100.00
V1 csr_hw_reset mbx_csr_hw_reset 5.000s 14.865us 5 5 100.00
V1 csr_rw mbx_csr_rw 5.000s 22.292us 20 20 100.00
V1 csr_bit_bash mbx_csr_bit_bash 5.000s 115.788us 5 5 100.00
V1 csr_aliasing mbx_csr_aliasing 5.000s 11.229us 5 5 100.00
V1 csr_mem_rw_with_rand_reset mbx_csr_mem_rw_with_rand_reset 5.000s 2.276us 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr mbx_csr_rw 5.000s 22.292us 20 20 100.00
mbx_csr_aliasing 5.000s 11.229us 5 5 100.00
V1 TOTAL 37 57 64.91
V2 mbx_stress mbx_stress 1.717m 22.693ms 2 2 100.00
mbx_stress_zero_delays 2.083m 1.944ms 2 2 100.00
V2 mbx_imbx_oob mbx_imbx_oob 48.000s 3.986ms 2 2 100.00
V2 alert_test mbx_alert_test 39.000s 12.519us 50 50 100.00
V2 tl_d_oob_addr_access mbx_tl_errors 5.000s 886.599ns 0 20 0.00
V2 tl_d_illegal_access mbx_tl_errors 5.000s 886.599ns 0 20 0.00
V2 tl_d_outstanding_access mbx_csr_hw_reset 5.000s 14.865us 5 5 100.00
mbx_csr_rw 5.000s 22.292us 20 20 100.00
mbx_csr_aliasing 5.000s 11.229us 5 5 100.00
mbx_same_csr_outstanding 5.000s 15.866us 20 20 100.00
V2 tl_d_partial_access mbx_csr_hw_reset 5.000s 14.865us 5 5 100.00
mbx_csr_rw 5.000s 22.292us 20 20 100.00
mbx_csr_aliasing 5.000s 11.229us 5 5 100.00
mbx_same_csr_outstanding 5.000s 15.866us 20 20 100.00
V2 TOTAL 76 96 79.17
V2S tl_intg_err mbx_sec_cm 39.000s 106.650us 5 5 100.00
mbx_tl_intg_err 5.000s 27.400us 0 20 0.00
V2S TOTAL 5 25 20.00
TOTAL 118 178 66.29

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
90.61 97.02 92.79 96.86 80.03 85.25 -- 98.54 63.09

Failure Buckets