OTBN Simulation Results

Friday May 02 2025 17:38:26 UTC

GitHub Revision: `c9ef9e5`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	43.000s	37.296us	1	1	100.00
V1	single_binary	otbn_single	1.950m	1.841ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	11.000s	35.386us	5	5	100.00
V1	csr_rw	otbn_csr_rw	8.000s	12.632us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	10.000s	512.117us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	9.000s	23.205us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	29.049us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	8.000s	12.632us	20	20	100.00
		otbn_csr_aliasing	9.000s	23.205us	5	5	100.00
V1	mem_walk	otbn_mem_walk	42.000s	16.199ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	18.000s	425.123us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.550m	292.702us	10	10	100.00
V2	multi_error	otbn_multi_err	1.033m	1.177ms	1	1	100.00
V2	back_to_back	otbn_multi	1.700m	419.035us	10	10	100.00
V2	stress_all	otbn_stress_all	7.583m	1.631ms	10	10	100.00
V2	lc_escalation	otbn_escalate	34.000s	87.264us	57	60	95.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	14.000s	24.363us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	17.000s	469.562us	10	10	100.00
V2	alert_test	otbn_alert_test	13.000s	37.603us	50	50	100.00
V2	intr_test	otbn_intr_test	9.000s	14.098us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	13.000s	106.888us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	13.000s	106.888us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	11.000s	35.386us	5	5	100.00
		otbn_csr_rw	8.000s	12.632us	20	20	100.00
		otbn_csr_aliasing	9.000s	23.205us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	32.073us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	11.000s	35.386us	5	5	100.00
		otbn_csr_rw	8.000s	12.632us	20	20	100.00
		otbn_csr_aliasing	9.000s	23.205us	5	5	100.00
		otbn_same_csr_outstanding	10.000s	32.073us	20	20	100.00
V2		TOTAL			243	246	98.78
V2S	mem_integrity	otbn_imem_err	19.000s	22.419us	10	10	100.00
		otbn_dmem_err	19.000s	125.890us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	17.000s	106.330us	5	5	100.00
		otbn_controller_ispr_rdata_err	15.000s	63.230us	5	5	100.00
		otbn_mac_bignum_acc_err	14.000s	21.173us	5	5	100.00
		otbn_urnd_err	14.000s	19.550us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	12.000s	36.133us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	11.000s	93.536us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	11.000s	25.412us	10	10	100.00
V2S	tl_intg_err	otbn_sec_cm	5.200m	1.279ms	3	5	60.00
		otbn_tl_intg_err	41.000s	234.716us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	33.000s	629.469us	15	20	75.00
V2S	prim_fsm_check	otbn_sec_cm	5.200m	1.279ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	5.200m	1.279ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	43.000s	37.296us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	19.000s	125.890us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	19.000s	22.419us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	41.000s	234.716us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	34.000s	87.264us	57	60	95.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	19.000s	22.419us	10	10	100.00
		otbn_dmem_err	19.000s	125.890us	15	15	100.00
		otbn_zero_state_err_urnd	14.000s	24.363us	5	5	100.00
		otbn_illegal_mem_acc	12.000s	36.133us	5	5	100.00
		otbn_sec_cm	5.200m	1.279ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	5.200m	1.279ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.950m	1.841ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	19.000s	22.419us	10	10	100.00
		otbn_dmem_err	19.000s	125.890us	15	15	100.00
		otbn_zero_state_err_urnd	14.000s	24.363us	5	5	100.00
		otbn_illegal_mem_acc	12.000s	36.133us	5	5	100.00
		otbn_sec_cm	5.200m	1.279ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	5.200m	1.279ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	34.000s	87.264us	57	60	95.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	19.000s	22.419us	10	10	100.00
		otbn_dmem_err	19.000s	125.890us	15	15	100.00
		otbn_zero_state_err_urnd	14.000s	24.363us	5	5	100.00
		otbn_illegal_mem_acc	12.000s	36.133us	5	5	100.00
		otbn_sec_cm	5.200m	1.279ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	5.200m	1.279ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.950m	1.841ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	13.000s	87.989us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	11.000s	36.516us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	58.000s	781.987us	4	5	80.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	58.000s	781.987us	4	5	80.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	15.000s	36.589us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	5.200m	1.279ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	5.200m	1.279ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	19.000s	89.006us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	5.200m	1.279ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	5.200m	1.279ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	47.485us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	16.000s	47.485us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	16.000s	119.277us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.950m	1.841ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.950m	1.841ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.950m	1.841ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.700m	419.035us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.950m	1.841ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.950m	1.841ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	17.000s	59.653us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	1.950m	1.841ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	5.200m	1.279ms	3	5	60.00
V2S		TOTAL			154	163	94.48
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	7.967m	4.186ms	4	10	40.00
V3		TOTAL			4	10	40.00
		TOTAL			567	585	96.92

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.11	99.64	96.00	99.73	93.12	93.52	100.00	98.18	100.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test otbn_stress_all_with_rand_reset has 4 failures.
  - 0.otbn_stress_all_with_rand_reset.48919182281023839724801203040021023107259288372111881739187846401288469464395
    Line 236, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1551475508 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1551475508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.otbn_stress_all_with_rand_reset.8076650064255662819659721719488915052144251128680884624029607477302805326997
    Line 310, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2068757927 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2068757927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 4 failures:
- Test otbn_passthru_mem_tl_intg_err has 4 failures.
  - 5.otbn_passthru_mem_tl_intg_err.112823089408662536055977712038533676772019368940630903658119609658739105349494
    Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/5.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @   3048232 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @   3048232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.otbn_passthru_mem_tl_intg_err.60597146614726334021371337307459149622019972792582668141259306443519254955562
    Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @   1012697 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @   1012697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

2.otbn_sec_cm.76926528865408667070650829620880844047609498998414462216062928419855922498733
Line 126, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 168380771 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 168380771 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @ 168380771 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @ 168380771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.otbn_sec_cm.31982521245776867448258753234036545861101981383519313479171855697000333133275
Line 92, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 14456027 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 14456027 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @  14456027 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @  14456027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status has 2 failures:

Test otbn_escalate has 2 failures.

24.otbn_escalate.15069767393003142282031748435163899582305033944623302542808771349654217536978
Line 103, in log /nightly/runs/scratch/master/otbn-sim-xcelium/24.otbn_escalate/latest/run.log

  UVM_ERROR @   9550123 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   9550123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

51.otbn_escalate.22611440656039652569675419667820344188030271052631112716833212423622800506054
Line 110, in log /nightly/runs/scratch/master/otbn-sim-xcelium/51.otbn_escalate/latest/run.log

  UVM_ERROR @   4218569 ps: (otbn_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register otbn_reg_block.status
  UVM_INFO @   4218569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:424) [otbn_single_vseq] Check failed exp_end_addr == cfg.model_agent_cfg.vif.stop_pc (* [*] vs * [*]) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.94634763762041185141093745537346312611829156119096600608245465564282354979264
    Line 313, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3388890404 ps: (otbn_base_vseq.sv:424) [uvm_test_top.env.virtual_sequencer.otbn_single_vseq] Check failed exp_end_addr == cfg.model_agent_cfg.vif.stop_pc (2512 [0x9d0] vs 2516 [0x9d4])
  UVM_INFO @ 3388890404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:
- Test otbn_sec_wipe_err has 1 failures.
  - 3.otbn_sec_wipe_err.17993886765041335378532433988055667621632101956006480859670450051857104884250
    Line 110, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_sec_wipe_err/latest/run.log
```
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 119277355 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @ 119277355 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @ 119277355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_rnd_if.sv,175): Assertion EdgePREFETCHINGToFULL_A has failed (* cycles, starting * PS) has 1 failures:

Test otbn_rnd_sec_cm has 1 failures.

4.otbn_rnd_sec_cm.42447602837330998786836435762099695351388597157459263035422648414211861699400
Line 131, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_rnd_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_rnd_if.sv,175): (time 548156364 PS) Assertion tb.dut.u_otbn_core.u_otbn_rnd.i_otbn_rnd_if.EdgePREFETCHINGToFULL_A has failed (2 cycles, starting 548116364 PS)
  UVM_ERROR @ 548156364 ps: (otbn_rnd_if.sv:175) [ASSERT FAILED] EdgePREFETCHINGToFULL_A
  UVM_INFO @ 548156364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 5.otbn_stress_all_with_rand_reset.80435154408233601659724005218187038976208684038109141594498708750393726622598
    Line 326, in log /nightly/runs/scratch/master/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2341305696 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 2341305696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:
- Test otbn_passthru_mem_tl_intg_err has 1 failures.
  - 7.otbn_passthru_mem_tl_intg_err.19458347348403185176745904369791546508121127004995422815168934118140412876133
    Line 92, in log /nightly/runs/scratch/master/otbn-sim-xcelium/7.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @  41357330 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  41357330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_scoreboard.sv:507) scoreboard [scoreboard] A fatal alert arrived * cycles ago and we still don't think it should have done. has 1 failures:
- Test otbn_escalate has 1 failures.
  - 49.otbn_escalate.92758246477327880022241562021451465889220512950712652958078992616813610319909
    Line 99, in log /nightly/runs/scratch/master/otbn-sim-xcelium/49.otbn_escalate/latest/run.log
```
  UVM_FATAL @ 165688245 ps: (otbn_scoreboard.sv:507) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] A fatal alert arrived 4000 cycles ago and we still don't think it should have done.
  UVM_INFO @ 165688245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```